TY - JOUR
T1 - A low complexity detection of discrete cross differences for fast H.264/AVC intra prediction
AU - Bharanitharan, K.
AU - Liu, Bin Da
AU - Yang, Jar Ferr
AU - Tsai, Wen Chih
N1 - Funding Information:
Manuscript received December 14, 2007; revised June 08, 2008. First published November 17, 2008. This work was supported in part by the National Science Council of Taiwan under Grants NSC95-2220-E-006-007 and NSC 96-2220-E-006-002. The associate editor coordinating the review of this manuscript and approving it for publication was Dr. Susanto Rahardja.
PY - 2008/11
Y1 - 2008/11
N2 - A low complexity fast mode decision algorithm for H.264/AVC intra prediction that uses discrete cross differences (DCD) to reduce the unlikely candidate modes in the RDO calculation is proposed. By using horizontal and vertical differences in different locations, the directions of the edges can be precisely detected. Experimental results show that the proposed fast mode decision algorithm reduces the encoding time by about 56%, with negligible loss of video quality. To realize the proposed algorithm, a VLSI design, which is comprised of a cross difference unit and direction detection unit, is implemented for the mode pre-selection stage of intra prediction. The design is synthesized using UMC 0.18 /im CMOS technology and simulated with Verilog-XL. The operating frequency of the synthesized core can exceed 50 MHz.
AB - A low complexity fast mode decision algorithm for H.264/AVC intra prediction that uses discrete cross differences (DCD) to reduce the unlikely candidate modes in the RDO calculation is proposed. By using horizontal and vertical differences in different locations, the directions of the edges can be precisely detected. Experimental results show that the proposed fast mode decision algorithm reduces the encoding time by about 56%, with negligible loss of video quality. To realize the proposed algorithm, a VLSI design, which is comprised of a cross difference unit and direction detection unit, is implemented for the mode pre-selection stage of intra prediction. The design is synthesized using UMC 0.18 /im CMOS technology and simulated with Verilog-XL. The operating frequency of the synthesized core can exceed 50 MHz.
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U2 - 10.1109/TMM.2008.2004904
DO - 10.1109/TMM.2008.2004904
M3 - Article
AN - SCOPUS:56549105469
SN - 1520-9210
VL - 10
SP - 1250
EP - 1260
JO - IEEE Transactions on Multimedia
JF - IEEE Transactions on Multimedia
IS - 7
M1 - 4668507
ER -