A low-cost and scalable test architecture for multi-core chips

Chun Chuan Chi; Cheng Wen Wu; Jin Fu Li

doi:10.1109/ETSYM.2010.5512784

A low-cost and scalable test architecture for multi-core chips

Chun Chuan Chi, Cheng Wen Wu, Jin Fu Li

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

Multi-core architecture has become a mainstream in modern processor and computation-intensive chips. A widely-used multi-core architecture contains identical cores. This paper proposes a low-cost and scalable test architecture for a multi-core chip with identical cores. The test architecture provides test scalability by using a two-dimensional pipelined test access mechanism (TAM). Also, some scan cells of the cores under test are reused as the pipeline registers of the TAM such that the area cost of the proposed test architecture is low. Experimental results show that the proposed test architecture only consumes about 2.6% area for a multi-core chip with 16 Advanced Encryption Standard (AES) cores. Also, the test time for 16 AES cores is only about 1.004 times of that for a single AES core.

Original language	English
Title of host publication	2010 15th IEEE European Test Symposium, ETS'10
Pages	30-35
Number of pages	6
DOIs	https://doi.org/10.1109/ETSYM.2010.5512784
Publication status	Published - 2010 Nov 3
Event	2010 15th IEEE European Test Symposium, ETS'10 - Prague, Czech Republic Duration: 2010 May 24 → 2010 May 28

Publication series

Name	2010 15th IEEE European Test Symposium, ETS'10

Conference

Conference	2010 15th IEEE European Test Symposium, ETS'10
Country	Czech Republic
City	Prague
Period	10-05-24 → 10-05-28

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ETSYM.2010.5512784

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Cite this

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