The median filter plays an important role in image processing for noise removing. To enhance the operating speed, hardware implementation of median filter on field programmable gate arrays (FPGA) or application specific IC (ASIC) are necessary and inevitable. This paper presents a low-cost and high-throughput hardware design for two-dimensional (2D) median filter. Two techniques are employed to reduce circuit area. One is the parallel three-valued sorting method for reducing the number of pipelined registers under constant speed, and the other is the functional sharing method used to implement median value sorting with the least number of comparisons. The proposed 2D median filter is implemented by two different synthesized methods. One is synthesized by Synopsys Design Compiler with the TSMC 90nm cell library (ASIC design) and the other is synthesized by Xilinx FPGA Virtex7 XC7VX690T (FPGA design). Experimental results show that the area cost of the proposed design is reduced more than 30% on average in comparison to the previous designs.
All Science Journal Classification (ASJC) codes
- Computer Science(all)
- Materials Science(all)