A low-cost, low-complexity, and memory-free architecture of novel recursive DFT and IDFT algorithms for DTMF application

Shin Chi Lai; Sheau Fang Lei; Wen Ho Juang; Ching Hsing Luo

doi:10.1109/TCSII.2010.2056413

A low-cost, low-complexity, and memory-free architecture of novel recursive DFT and IDFT algorithms for DTMF application

Shin Chi Lai, Sheau Fang Lei, Wen Ho Juang, Ching Hsing Luo

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

11 Citations (Scopus)

Abstract

A low-computational complexity and low-cost recursive discrete Fourier transform (RDFT) design using the Chinese remainder theorem is proposed in this brief. The proposed algorithm reduces multiplications by 74% and additions by 73% compared to the latest RDFT algorithms. For computing the 212- and 106-point DFT coefficients, the proposed design can shorten computing cycles by 47% compared with the latest architectures. The hardware resources for the proposed design only require 2 multipliers and 12 adders. The coefficient read-only memory storing the sine and cosine values can be reduced by 100% compared with other recursive algorithms. Therefore, the proposed algorithm is more suitable than other very large scale integration realizations.

Original language	English
Article number	5571862
Pages (from-to)	711-715
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	57
Issue number	9
DOIs	https://doi.org/10.1109/TCSII.2010.2056413
Publication status	Published - 2010 Sep

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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title = "A low-cost, low-complexity, and memory-free architecture of novel recursive DFT and IDFT algorithms for DTMF application",

abstract = "A low-computational complexity and low-cost recursive discrete Fourier transform (RDFT) design using the Chinese remainder theorem is proposed in this brief. The proposed algorithm reduces multiplications by 74% and additions by 73% compared to the latest RDFT algorithms. For computing the 212- and 106-point DFT coefficients, the proposed design can shorten computing cycles by 47% compared with the latest architectures. The hardware resources for the proposed design only require 2 multipliers and 12 adders. The coefficient read-only memory storing the sine and cosine values can be reduced by 100% compared with other recursive algorithms. Therefore, the proposed algorithm is more suitable than other very large scale integration realizations.",

author = "Lai, {Shin Chi} and Lei, {Sheau Fang} and Juang, {Wen Ho} and Luo, {Ching Hsing}",

note = "Funding Information: Manuscript received November 19, 2009; revised February 3, 2010 and April 19, 2010; accepted May 20, 2010. Date of current version September 15, 2010. This work was supported in part by the National Science Council, Taiwan, under Grant NSC 98-2220-E006-005. This paper was recommended by Associate Editor T. Zhang.",

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N1 - Funding Information: Manuscript received November 19, 2009; revised February 3, 2010 and April 19, 2010; accepted May 20, 2010. Date of current version September 15, 2010. This work was supported in part by the National Science Council, Taiwan, under Grant NSC 98-2220-E006-005. This paper was recommended by Associate Editor T. Zhang.

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