A low-cost SOC debug platform based on on-chip test architectures

Kuen-Jong Lee, Si Yuan Liang, Alan Su

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

While the complexity of System-on-a-Chip (SoC) design keeps growing rapidly today the need for an efficient approach to catch design errors at silicon stage has become an urgent issue. In this paper we present a platform for silicon debugging that makes use of an existing test architecture and thus can provide many powerful debug features while requiring very low extra overhead. It supports multi-core debugging for general purpose cores in an SOC chip with the capabilities of on-line tracing, hardware breakpoint insertion and cycle-based stepping. An automatic design tool is also developed to cooperate with the debug platform. Together users can easily control debug operations and examine trace results to efficiently identify the root cause of failures in the silicon.

Original languageEnglish
Title of host publicationProceedings - IEEE International SOC Conference, SOCC 2009
Pages161-164
Number of pages4
DOIs
Publication statusPublished - 2009 Dec 1
EventIEEE International SOC Conference, SOCC 2009 - Belfast, Ireland
Duration: 2009 Sep 92009 Sep 11

Publication series

NameProceedings - IEEE International SOC Conference, SOCC 2009

Other

OtherIEEE International SOC Conference, SOCC 2009
CountryIreland
CityBelfast
Period09-09-0909-09-11

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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