A low-cost stimulus design for linearity test in SAR ADCs

An Sheng Chao, Cheng Wu Lin, Hsin Wen Ting, Soon-Jyh Chang

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

The proposed stimulus design for linearity test is embedded in a differential successive approximation register analog-to-digital converter (SAR ADC), i.e. a design for testability (DFT). The proposed DFT is compatible to the pattern generator (PG) and output response analyzer (ORA) with the cost of 12.4-% area of the SAR ADC. The 10-bit SAR ADC prototype is verified in a 0.18-μm CMOS technology and the measured differential nonlinearity (DNL) error is between -0.386 and 0.281 LSB at 1-MS/s.

Original languageEnglish
Pages (from-to)538-545
Number of pages8
JournalIEICE Transactions on Electronics
VolumeE97-C
Issue number6
DOIs
Publication statusPublished - 2014 Jan 1

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Digital to analog conversion
Design for testability
Costs

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Chao, An Sheng ; Lin, Cheng Wu ; Ting, Hsin Wen ; Chang, Soon-Jyh. / A low-cost stimulus design for linearity test in SAR ADCs. In: IEICE Transactions on Electronics. 2014 ; Vol. E97-C, No. 6. pp. 538-545.
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A low-cost stimulus design for linearity test in SAR ADCs. / Chao, An Sheng; Lin, Cheng Wu; Ting, Hsin Wen; Chang, Soon-Jyh.

In: IEICE Transactions on Electronics, Vol. E97-C, No. 6, 01.01.2014, p. 538-545.

Research output: Contribution to journalArticle

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