A low-cost stimulus design for linearity test in SAR ADCs

An Sheng Chao, Cheng Wu Lin, Hsin Wen Ting, Soon Jyh Chang

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)


The proposed stimulus design for linearity test is embedded in a differential successive approximation register analog-to-digital converter (SAR ADC), i.e. a design for testability (DFT). The proposed DFT is compatible to the pattern generator (PG) and output response analyzer (ORA) with the cost of 12.4-% area of the SAR ADC. The 10-bit SAR ADC prototype is verified in a 0.18-μm CMOS technology and the measured differential nonlinearity (DNL) error is between -0.386 and 0.281 LSB at 1-MS/s.

Original languageEnglish
Pages (from-to)538-545
Number of pages8
JournalIEICE Transactions on Electronics
Issue number6
Publication statusPublished - 2014 Jun

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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