TY - JOUR
T1 - A low-cost VLSI architecture for fault-tolerant fusion center in wireless sensor networks
AU - Chen, Pei Yin
AU - Chang, Li Yuan
AU - Wang, Tsang Yi
N1 - Funding Information:
Manuscript received December 07, 2008; revised April 13, 2009. First published June 19, 2009; current version published April 09, 2010. This work was supported in part by the National Science Council, Taiwan, under Grant NSC 96-2221-E-006-027-MY3 and Grant NSC 98-2220-E-006-016. This work made use of Shared Facilities supported by the Program of Top 100 Universities Advancement, Ministry of Education, Taiwan. This paper was recommended by Asssociate Editor N. K. Jha.
PY - 2010
Y1 - 2010
N2 - A fault-tolerant distributed decision fusion in the presence of sensor faults via collaborative sensor fault detection (CSFD) was proposed in our previous research. The scheme can identify the faulty nodes efficiently and improve the performance of the decision fusion significantly. It achieves very good performance at the expense of such extensive computations as exponent and multiplication/division in the detecting process. In many real-time WSN applications, the fusion center might be implemented in an ASIC and included in a standalone device. Therefore, a simple and efficient decision fusion scheme requiring lower hardware cost and power consumption is extremely desired. In this paper, we propose the approximated collaborative sensor fault detection (ACSFD) scheme and its VLSI architecture. Given the low circuit complexity, it is suitable for hardware implementation. The ACSFD circuit contains 9265 gates and requires a core size of 368 × 358 μm2 by using TSMC 0.18 μm cell library. It can operate at a clock rate of 102 MHz with a power consumption of 2.516 mW. Simulation results indicate that ACSFD performs better in fault tolerance than the conventional approach.
AB - A fault-tolerant distributed decision fusion in the presence of sensor faults via collaborative sensor fault detection (CSFD) was proposed in our previous research. The scheme can identify the faulty nodes efficiently and improve the performance of the decision fusion significantly. It achieves very good performance at the expense of such extensive computations as exponent and multiplication/division in the detecting process. In many real-time WSN applications, the fusion center might be implemented in an ASIC and included in a standalone device. Therefore, a simple and efficient decision fusion scheme requiring lower hardware cost and power consumption is extremely desired. In this paper, we propose the approximated collaborative sensor fault detection (ACSFD) scheme and its VLSI architecture. Given the low circuit complexity, it is suitable for hardware implementation. The ACSFD circuit contains 9265 gates and requires a core size of 368 × 358 μm2 by using TSMC 0.18 μm cell library. It can operate at a clock rate of 102 MHz with a power consumption of 2.516 mW. Simulation results indicate that ACSFD performs better in fault tolerance than the conventional approach.
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U2 - 10.1109/TCSI.2009.2025854
DO - 10.1109/TCSI.2009.2025854
M3 - Article
AN - SCOPUS:77951025450
VL - 57
SP - 803
EP - 813
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
SN - 1057-7122
IS - 4
M1 - 5089461
ER -