In this paper, we present a low dropout voltage regulator (LDO) which can be programmed to generate four output voltages (3.3 V, 2.5 V, 1.8 V, and 0 V) by the external control signals. Between the error amplifier and the power transistor, we place a simple buffer so that the power supply rejection (PSR) of LDO can be improved. The design specification of the maximum load current is 100mA. The proposed LDO is designed by the 0.35μm CMOS 2P4M process technology and simulated by HSPICE. Simulation results show that the maximum transient-output variation (overshoot voltage) is about 50 mV with full-load step change of 100 mA and the PSR is larger than 60dB for different output voltages. Therefore, the proposed LDO can be applied for power management systems in system-on-chip (SOC), where the output voltage can be changed by control logic to optimize the power consumption of supplied device.