A Low Energy Consumption 10-Bit 100kS/s SAR ADC with Timing Control Adaptive Window

Chih Yuan Kung, Chun Po Huang, Chia Chuan Li, Soon Jyh Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

This paper presents a 0.35 V 100 kS/s 10-bit successive approximation register (SAR) ADC with adaptive window (AW) in 90 nm CMOS. The SAR ADC uses the transient information of the latch comparator to create redundancy ranges. Furthermore, the proposed technique also uses the transient information to produce AW for each bit which can significantly reduce the power consumption of the comparator, the DAC settling time and also digital control logic. Last but not least, the timing control window can also avoid ADC from encountering meta-stability. The measurement result achieves an SNDR of 57.18 dB, an ENOB of 9.2 bits, a power consumption of 74 nW, and a resulting FoM of 1.25 fJ/conv.-step.

Original languageEnglish
Title of host publication2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538648810
DOIs
Publication statusPublished - 2018 Apr 26
Event2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy
Duration: 2018 May 272018 May 30

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2018-May
ISSN (Print)0271-4310

Other

Other2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
CountryItaly
CityFlorence
Period18-05-2718-05-30

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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