TY - JOUR
T1 - A low-latency compression architecture for memory i/o link on GPGPU
AU - Lu, Meng Yang
AU - Lai, Yu An
AU - Kuo, Chih Hung
PY - 2019/10
Y1 - 2019/10
N2 - With the advance of contemporary computer architectures, there is a continuously growing performance gap between processors and memories. Data compression is a promising approach to resolve this issue by reducing the data size. On general-purpose graphics processing unit (GPGPU), many parallel computing applications have large amounts of floating-point data. In this paper, we propose an innovative compression algorithm with low latency by exploiting regular data patterns. By integrating the proposed architecture with the memory controller, the GPU can averagely reduce 44.46% of the memory bandwidth usage, and reduce 44.34% of the energy consumption.
AB - With the advance of contemporary computer architectures, there is a continuously growing performance gap between processors and memories. Data compression is a promising approach to resolve this issue by reducing the data size. On general-purpose graphics processing unit (GPGPU), many parallel computing applications have large amounts of floating-point data. In this paper, we propose an innovative compression algorithm with low latency by exploiting regular data patterns. By integrating the proposed architecture with the memory controller, the GPU can averagely reduce 44.46% of the memory bandwidth usage, and reduce 44.34% of the energy consumption.
UR - http://www.scopus.com/inward/record.url?scp=85076878760&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85076878760&partnerID=8YFLogxK
U2 - 10.6329/CIEE.201910_26(5).0003
DO - 10.6329/CIEE.201910_26(5).0003
M3 - Article
AN - SCOPUS:85076878760
SN - 1812-3031
VL - 26
SP - 203
EP - 210
JO - International Journal of Electrical Engineering
JF - International Journal of Electrical Engineering
IS - 5
ER -
