A low-power design methodology for sigma-delta modulators with relaxation of required circuit specifications

Jia Hua Hong, Ming Chun Liang, Jing Yi Wong, Shuenn Yuh Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A design methodology of high-order sigma-delta modulators (SDMs) with relaxation of required circuit specifications is proposed to reduce the required power consumption and to be suitable for the nano-scale circuit. According to the proposed design flow, more relaxed circuit specifications can be selected so that designers can maintain system performance. One design example is employed to verify the proposed design flow. Circuit-level simulation reveals that the power consumption is lower under the same system performance compared with a conventional design flow. The circuits are implement with TSMC 90nm 1P9M CMOS process and the measured signal-to-noise distortion ratio (SNDR) is 64.5 dB, with a power consumption of 303μW.

Original languageEnglish
Title of host publication2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
DOIs
Publication statusPublished - 2013 Aug 15
Event2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 - Hsinchu, Taiwan
Duration: 2013 Apr 222013 Apr 24

Publication series

Name2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013

Other

Other2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
CountryTaiwan
CityHsinchu
Period13-04-2213-04-24

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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