A low-power IP design of viterbi decoder with dynamic threshold setting

Yi Ming Lin, Wan Ching Liu, Li Yuan Chang, Chih Yuan Lien, Pei-Yin Chen, Shung Chih Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

In this paper, a low-power design of Viterbi de-coder is presented. Based on the adaptive Viterbi algorithm, we use a dynamic setting method to set various threshold values for different decoding stages under a particular SNR and effi-cient reduce the average number of survivor paths. Further-more, a flexible soft intellectual property core and an auxiliary software system for low-power Viterbi decoder are proposed. In the VLSI realization, we apply the clock-gating technique to disable the activation of registers for nonsurvivor paths. Hence, the power consumption can be reduced. Compared with others, our design requires the lower power consumption for the same SNR condition.

Original languageEnglish
Title of host publicationISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
Subtitle of host publicationNano-Bio Circuit Fabrics and Systems
Pages585-588
Number of pages4
DOIs
Publication statusPublished - 2010
Event2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France
Duration: 2010 May 302010 Jun 2

Other

Other2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
CountryFrance
CityParis
Period10-05-3010-06-02

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A low-power IP design of viterbi decoder with dynamic threshold setting'. Together they form a unique fingerprint.

Cite this