A low-power LFSR architecture

Tsung Chu Huang; Kuen-Jong Lee

doi:10.1109/ATS.2001.990337

A low-power LFSR architecture

Tsung Chu Huang, Kuen-Jong Lee

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

6 Citations (Scopus)

Abstract

LFSRs are widely used in Built-In Self-Test (BIST) environment. A multiphase technique proposed to reduce the data transitions (DTs) in both the LFSR and the circuit under test has been found to have some limitations. This paper discusses the development of a low-power multiphase clock generator and the employment of static demultiplexers. It also proposes a hybrid design to reduce the power.

Original language	English
Article number	80
Number of pages	1
Journal	Proceedings of the Asian Test Symposium
DOIs	https://doi.org/10.1109/ATS.2001.990337
Publication status	Published - 2001 Jan 1

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/ATS.2001.990337

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@article{114b38a56e5649a2b1a801aacdad6935,

title = "A low-power LFSR architecture",

abstract = "LFSRs are widely used in Built-In Self-Test (BIST) environment. A multiphase technique proposed to reduce the data transitions (DTs) in both the LFSR and the circuit under test has been found to have some limitations. This paper discusses the development of a low-power multiphase clock generator and the employment of static demultiplexers. It also proposes a hybrid design to reduce the power.",

author = "Huang, {Tsung Chu} and Kuen-Jong Lee",

year = "2001",

month = jan,

day = "1",

doi = "10.1109/ATS.2001.990337",

language = "English",

journal = "Proceedings of the Asian Test Symposium",

issn = "1081-7735",

publisher = "IEEE Computer Society",

}

TY - JOUR

T1 - A low-power LFSR architecture

AU - Huang, Tsung Chu

AU - Lee, Kuen-Jong

PY - 2001/1/1

Y1 - 2001/1/1

N2 - LFSRs are widely used in Built-In Self-Test (BIST) environment. A multiphase technique proposed to reduce the data transitions (DTs) in both the LFSR and the circuit under test has been found to have some limitations. This paper discusses the development of a low-power multiphase clock generator and the employment of static demultiplexers. It also proposes a hybrid design to reduce the power.

AB - LFSRs are widely used in Built-In Self-Test (BIST) environment. A multiphase technique proposed to reduce the data transitions (DTs) in both the LFSR and the circuit under test has been found to have some limitations. This paper discusses the development of a low-power multiphase clock generator and the employment of static demultiplexers. It also proposes a hybrid design to reduce the power.

UR - http://www.scopus.com/inward/record.url?scp=0035701605&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0035701605&partnerID=8YFLogxK

U2 - 10.1109/ATS.2001.990337

DO - 10.1109/ATS.2001.990337

M3 - Article

AN - SCOPUS:0035701605

JO - Proceedings of the Asian Test Symposium

JF - Proceedings of the Asian Test Symposium

SN - 1081-7735

M1 - 80

ER -

A low-power LFSR architecture

Abstract

All Science Journal Classification (ASJC) codes

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