Abstract
LFSRs are widely used in Built-In Self-Test (BIST) environment. A multiphase technique proposed to reduce the data transitions (DTs) in both the LFSR and the circuit under test has been found to have some limitations. This paper discusses the development of a low-power multiphase clock generator and the employment of static demultiplexers. It also proposes a hybrid design to reduce the power.
Original language | English |
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Article number | 80 |
Pages (from-to) | 470 |
Number of pages | 1 |
Journal | Proceedings of the Asian Test Symposium |
DOIs | |
Publication status | Published - 2001 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering