Abstract
A novel structure with an additional current path is adopted in the proposed circuit to reduce the power consumption. Threshold voltage variations of TFTs and VDD I-R drops are compensated effectively. The power consumption is reduced by 12.95% greater than the compared circuit without the additional current source structure.
Original language | English |
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Pages (from-to) | 66-69 |
Number of pages | 4 |
Journal | Digest of Technical Papers - SID International Symposium |
Volume | 54 |
Issue number | 1 |
DOIs | |
Publication status | Published - 2023 |
Event | SID International Symposium Digest of Technical Papers, 2023 - Los Angeles, United States Duration: 2023 May 21 → 2023 May 26 |
All Science Journal Classification (ASJC) codes
- General Engineering