A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach

Hui Chin Tseng, Chi Sheng Lin, Hsin Hung Ou, Bin Da Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

In this paper, a 6-bit 300-MSample/s(MS/s) flash analog-to-digital converter (ADC) with a novel complementary average-value (CAV) approach is proposed. Input signal is pre-processed and then steered to be compared with a fixed reference voltage level, which greatly simplifies the comparator design and thus power consumption is reduced. In addition, rail-to-rail input range can be achieved by the proposed CAV technique, and the offset as well as bubble errors can therefore be minimized as a result of similar operation condition arrangement of the comparators. Simulated with TSMC 1P5M 0.25 μm process parameters, the results show that INL < ±0.4 LSB and DNL < ±0.1 LSB, and SNDR of 32.7dB can be achieved. The converter consumes 35mW at 2.5 V power supply and the power efficiency of this converter is only 3.3pJ/conv-step which compares favorably with other published results.

Original languageEnglish
Title of host publicationProceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04
Pages252-256
Number of pages5
Publication statusPublished - 2004 Dec 1
EventProceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04 - Newport Beach, CA, United States
Duration: 2004 Aug 92004 Aug 11

Publication series

NameProceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04

Other

OtherProceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04
CountryUnited States
CityNewport Beach, CA
Period04-08-0904-08-11

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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