A Low-Power Rail-to-Rail 6-bit Flash ADC Based on a Novel Complementary Average-Value Approach

Hui Chin Tseng; Chi Sheng Lin; Hsin Hung Ou; Bin-Da Liu

doi:10.1109/LPE.2004.241033

A Low-Power Rail-to-Rail 6-bit Flash ADC Based on a Novel Complementary Average-Value Approach

Hui Chin Tseng, Chi Sheng Lin, Hsin Hung Ou, Bin-Da Liu

Department of Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

1 Citation (Scopus)

Abstract

In this paper, a 6-bit 300-MSample/s(MS/s) flash analog-to-digital converter (ADC) with a novel complementary average-value (CAV) approach is proposed. Input signal is pre-processed and then steered to be compared with a fixed reference voltage level, which greatly simplifies the comparator design and thus power consumption is reduced. In addition, rail-to-rail input range can be achieved by the proposed CAV technique, and the offset as well as bubble errors can therefore be minimized as a result of similar operation condition arrangement of the comparators. Simulated with TSMC 1P5M 0.25 μm process parameters, the results show that INL < ±0.4 LSB and DNL < ±0.1 LSB, and SNDR of 32.7dB can be achieved. The converter consumes 35mW at 2.5 V power supply and the power efficiency of this converter is only 3.3pJ/conv-step which compares favorably with other published results.

Original language	English
Article number	1349346
Pages (from-to)	252-256
Number of pages	5
Journal	Proceedings of the International Symposium on Low Power Electronics and Design
Volume	2004-January
Issue number	January
DOIs	https://doi.org/10.1109/LPE.2004.241033
Publication status	Published - 2004 Jan 1
Event	2004 International Symposium on Low Power Electronics and Design, ISLPED 2004 - Newport Beach, United States Duration: 2004 Aug 9 → 2004 Aug 11

All Science Journal Classification (ASJC) codes

General Engineering

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10.1109/LPE.2004.241033

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title = "A Low-Power Rail-to-Rail 6-bit Flash ADC Based on a Novel Complementary Average-Value Approach",

abstract = "In this paper, a 6-bit 300-MSample/s(MS/s) flash analog-to-digital converter (ADC) with a novel complementary average-value (CAV) approach is proposed. Input signal is pre-processed and then steered to be compared with a fixed reference voltage level, which greatly simplifies the comparator design and thus power consumption is reduced. In addition, rail-to-rail input range can be achieved by the proposed CAV technique, and the offset as well as bubble errors can therefore be minimized as a result of similar operation condition arrangement of the comparators. Simulated with TSMC 1P5M 0.25 μm process parameters, the results show that INL < ±0.4 LSB and DNL < ±0.1 LSB, and SNDR of 32.7dB can be achieved. The converter consumes 35mW at 2.5 V power supply and the power efficiency of this converter is only 3.3pJ/conv-step which compares favorably with other published results.",

author = "Tseng, {Hui Chin} and Lin, {Chi Sheng} and Ou, {Hsin Hung} and Bin-Da Liu",

year = "2004",

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journal = "Proceedings of the International Symposium on Low Power Electronics and Design",

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note = "2004 International Symposium on Low Power Electronics and Design, ISLPED 2004 ; Conference date: 09-08-2004 Through 11-08-2004",

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A Low-Power Rail-to-Rail 6-bit Flash ADC Based on a Novel Complementary Average-Value Approach. / Tseng, Hui Chin; Lin, Chi Sheng; Ou, Hsin Hung et al.
In: Proceedings of the International Symposium on Low Power Electronics and Design, Vol. 2004-January, No. January, 1349346, 01.01.2004, p. 252-256.

Research output: Contribution to journal › Conference article › peer-review

TY - JOUR

T1 - A Low-Power Rail-to-Rail 6-bit Flash ADC Based on a Novel Complementary Average-Value Approach

AU - Tseng, Hui Chin

AU - Lin, Chi Sheng

AU - Ou, Hsin Hung

AU - Liu, Bin-Da

PY - 2004/1/1

Y1 - 2004/1/1

N2 - In this paper, a 6-bit 300-MSample/s(MS/s) flash analog-to-digital converter (ADC) with a novel complementary average-value (CAV) approach is proposed. Input signal is pre-processed and then steered to be compared with a fixed reference voltage level, which greatly simplifies the comparator design and thus power consumption is reduced. In addition, rail-to-rail input range can be achieved by the proposed CAV technique, and the offset as well as bubble errors can therefore be minimized as a result of similar operation condition arrangement of the comparators. Simulated with TSMC 1P5M 0.25 μm process parameters, the results show that INL < ±0.4 LSB and DNL < ±0.1 LSB, and SNDR of 32.7dB can be achieved. The converter consumes 35mW at 2.5 V power supply and the power efficiency of this converter is only 3.3pJ/conv-step which compares favorably with other published results.

AB - In this paper, a 6-bit 300-MSample/s(MS/s) flash analog-to-digital converter (ADC) with a novel complementary average-value (CAV) approach is proposed. Input signal is pre-processed and then steered to be compared with a fixed reference voltage level, which greatly simplifies the comparator design and thus power consumption is reduced. In addition, rail-to-rail input range can be achieved by the proposed CAV technique, and the offset as well as bubble errors can therefore be minimized as a result of similar operation condition arrangement of the comparators. Simulated with TSMC 1P5M 0.25 μm process parameters, the results show that INL < ±0.4 LSB and DNL < ±0.1 LSB, and SNDR of 32.7dB can be achieved. The converter consumes 35mW at 2.5 V power supply and the power efficiency of this converter is only 3.3pJ/conv-step which compares favorably with other published results.

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ER -

A Low-Power Rail-to-Rail 6-bit Flash ADC Based on a Novel Complementary Average-Value Approach

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