In this paper, a 6-bit 300-MSample/s(MS/s) flash analog-to-digital converter (ADC) with a novel complementary average-value (CAV) approach is proposed. Input signal is pre-processed and then steered to be compared with a fixed reference voltage level, which greatly simplifies the comparator design and thus power consumption is reduced. In addition, rail-to-rail input range can be achieved by the proposed CAV technique, and the offset as well as bubble errors can therefore be minimized as a result of similar operation condition arrangement of the comparators. Simulated with TSMC 1P5M 0.25 μm process parameters, the results show that INL < ±0.4 LSB and DNL < ±0.1 LSB, and SNDR of 32.7dB can be achieved. The converter consumes 35mW at 2.5 V power supply and the power efficiency of this converter is only 3.3pJ/conv-step which compares favorably with other published results.
|Number of pages||5|
|Journal||Proceedings of the International Symposium on Low Power Electronics and Design|
|Publication status||Published - 2004 Jan 1|
|Event||2004 International Symposium on Low Power Electronics and Design, ISLPED 2004 - Newport Beach, United States|
Duration: 2004 Aug 9 → 2004 Aug 11
All Science Journal Classification (ASJC) codes