A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach

Hui Chin Tseng; Chi Sheng Lin; Hsin Hung Ou; Bin Da Liu

A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach

Hui Chin Tseng, Chi Sheng Lin, Hsin Hung Ou, Bin Da Liu

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

In this paper, a 6-bit 300-MSample/s(MS/s) flash analog-to-digital converter (ADC) with a novel complementary average-value (CAV) approach is proposed. Input signal is pre-processed and then steered to be compared with a fixed reference voltage level, which greatly simplifies the comparator design and thus power consumption is reduced. In addition, rail-to-rail input range can be achieved by the proposed CAV technique, and the offset as well as bubble errors can therefore be minimized as a result of similar operation condition arrangement of the comparators. Simulated with TSMC 1P5M 0.25 μm process parameters, the results show that INL < ±0.4 LSB and DNL < ±0.1 LSB, and SNDR of 32.7dB can be achieved. The converter consumes 35mW at 2.5 V power supply and the power efficiency of this converter is only 3.3pJ/conv-step which compares favorably with other published results.

Original language	English
Title of host publication	Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04
Pages	252-256
Number of pages	5
Publication status	Published - 2004 Dec 1
Event	Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04 - Newport Beach, CA, United States Duration: 2004 Aug 9 → 2004 Aug 11

Publication series

Name	Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04

Other

Other	Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04
Country	United States
City	Newport Beach, CA
Period	04-08-09 → 04-08-11

All Science Journal Classification (ASJC) codes

Engineering(all)

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Cite this

Tseng, Hui Chin ; Lin, Chi Sheng ; Ou, Hsin Hung ; Liu, Bin Da. / A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach. Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04. 2004. pp. 252-256 (Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04).

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title = "A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach",

abstract = "In this paper, a 6-bit 300-MSample/s(MS/s) flash analog-to-digital converter (ADC) with a novel complementary average-value (CAV) approach is proposed. Input signal is pre-processed and then steered to be compared with a fixed reference voltage level, which greatly simplifies the comparator design and thus power consumption is reduced. In addition, rail-to-rail input range can be achieved by the proposed CAV technique, and the offset as well as bubble errors can therefore be minimized as a result of similar operation condition arrangement of the comparators. Simulated with TSMC 1P5M 0.25 μm process parameters, the results show that INL < ±0.4 LSB and DNL < ±0.1 LSB, and SNDR of 32.7dB can be achieved. The converter consumes 35mW at 2.5 V power supply and the power efficiency of this converter is only 3.3pJ/conv-step which compares favorably with other published results.",

author = "Tseng, {Hui Chin} and Lin, {Chi Sheng} and Ou, {Hsin Hung} and Liu, {Bin Da}",

year = "2004",

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series = "Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04",

pages = "252--256",

booktitle = "Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04",

note = "Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04 ; Conference date: 09-08-2004 Through 11-08-2004",

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Tseng, HC, Lin, CS, Ou, HH & Liu, BD 2004, A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach. in Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04. Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04, pp. 252-256, Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04, Newport Beach, CA, United States, 04-08-09.

A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach. / Tseng, Hui Chin; Lin, Chi Sheng; Ou, Hsin Hung; Liu, Bin Da.

Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04. 2004. p. 252-256 (Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - In this paper, a 6-bit 300-MSample/s(MS/s) flash analog-to-digital converter (ADC) with a novel complementary average-value (CAV) approach is proposed. Input signal is pre-processed and then steered to be compared with a fixed reference voltage level, which greatly simplifies the comparator design and thus power consumption is reduced. In addition, rail-to-rail input range can be achieved by the proposed CAV technique, and the offset as well as bubble errors can therefore be minimized as a result of similar operation condition arrangement of the comparators. Simulated with TSMC 1P5M 0.25 μm process parameters, the results show that INL < ±0.4 LSB and DNL < ±0.1 LSB, and SNDR of 32.7dB can be achieved. The converter consumes 35mW at 2.5 V power supply and the power efficiency of this converter is only 3.3pJ/conv-step which compares favorably with other published results.

AB - In this paper, a 6-bit 300-MSample/s(MS/s) flash analog-to-digital converter (ADC) with a novel complementary average-value (CAV) approach is proposed. Input signal is pre-processed and then steered to be compared with a fixed reference voltage level, which greatly simplifies the comparator design and thus power consumption is reduced. In addition, rail-to-rail input range can be achieved by the proposed CAV technique, and the offset as well as bubble errors can therefore be minimized as a result of similar operation condition arrangement of the comparators. Simulated with TSMC 1P5M 0.25 μm process parameters, the results show that INL < ±0.4 LSB and DNL < ±0.1 LSB, and SNDR of 32.7dB can be achieved. The converter consumes 35mW at 2.5 V power supply and the power efficiency of this converter is only 3.3pJ/conv-step which compares favorably with other published results.

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