TY - GEN
T1 - A Low Power Readout Circuit for a Tri-axial Piezoelectric MEMS Accelerometer
AU - Ciou, Sin Yu
AU - Chang, Soon Jyh
N1 - Funding Information:
ACKNOWLEDGMENT This work was supported by Ministry of Science and Technology of Taiwan under grant MOST-110-2218-E-006-021. The authors would like to express their gratitude to Taiwan Semiconductor Research Institute (TSRI), Taiwan, for the chip fabrication and measurement support.
Funding Information:
This work was supported in part by the grant MOST 110-2218-E-006-021 from National Science and Technology Council (NSTC), Taiwan.
Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - This paper presents a low power readout circuit for a tri-axial piezoelectric MEMS accelerometer. The readout circuit is composed of a successive approximation register (SAR) analog-to-digital converter (ADC) and an analog front-end, including transimpedance amplifier (TIA), low-pass filter and notch filter. The proposed TIA converts the sensed current signals into voltage signals, which is amplified and filtered in the later stages. The sample-and-hold circuit of the SAR ADC is replaced with the proposed simultaneous sampling circuit to reserve the correlation of the tri-axial signals. It not only saves the chip area but also reduces the loading of the previous stage. The proof-of-concept prototype was fabricated in TSMC 0.18- μ m CMOS technology. At a 1.8-V supply and 100-kS/s sampling rate, the readout circuit consumes 0.196 mW and achieves the sensing range of ±10 g with the sensitivity of 173.43 mV/g and the nonlinearity of 0.43%. The readout core occupies an area of 3.65 mm2.
AB - This paper presents a low power readout circuit for a tri-axial piezoelectric MEMS accelerometer. The readout circuit is composed of a successive approximation register (SAR) analog-to-digital converter (ADC) and an analog front-end, including transimpedance amplifier (TIA), low-pass filter and notch filter. The proposed TIA converts the sensed current signals into voltage signals, which is amplified and filtered in the later stages. The sample-and-hold circuit of the SAR ADC is replaced with the proposed simultaneous sampling circuit to reserve the correlation of the tri-axial signals. It not only saves the chip area but also reduces the loading of the previous stage. The proof-of-concept prototype was fabricated in TSMC 0.18- μ m CMOS technology. At a 1.8-V supply and 100-kS/s sampling rate, the readout circuit consumes 0.196 mW and achieves the sensing range of ±10 g with the sensitivity of 173.43 mV/g and the nonlinearity of 0.43%. The readout core occupies an area of 3.65 mm2.
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U2 - 10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134216
DO - 10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134216
M3 - Conference contribution
AN - SCOPUS:85163024999
T3 - 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings
BT - 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023
Y2 - 17 April 2023 through 20 April 2023
ER -