A low-power RF front-end with merged LNA, differential power splitter, and quadrature mixer for IEEE 802.15.4 (ZigBee) applications

Shuenn-Yuh Lee, Liang Hung Wang, Tsung Yen Chen, Chih Tao Yu

Research output: Contribution to conferencePaper

10 Citations (Scopus)

Abstract

A 2.4 GHz fully integrated CMOS RF front-end with low-noise amplifier (LNA), differential power splitter (DPS), and quadrature mixer based on current-reused folded architecture is proposed. The circuit has been implemented to fit the specifications of IEEE 802.15.4 2.4 GHz standard. To address the low power consumption issue, the active differential power splitter is directly stacked upon the LNA to allow the reuse of the DC bias current. The folded structure is implemented by using the PMOS device as the quadrature mixer to achieve low flicker and thermal noise, simultaneously. Both the LNA and the DPS are biased in the subthreshold region, which can offer superior gain per current consumption as compared with operation in the strong-inversion region. The chip is fabricated in the 0.18 μm CMOS process with an area of 1.69 mm 2 at a supply voltage of 1.2 V and power consumption of 1.08 mW. Based on the measurement results, the conversion gain of 20.5 dB and S11 of 17 dB can be obtained, respectively. Moreover, the IIP3 in the whole chip is 7.8 dBm, and the total double-side band noise figure is 13.2 dB.

Original languageEnglish
Pages1492-1495
Number of pages4
DOIs
Publication statusPublished - 2012 Sep 28
Event2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
Duration: 2012 May 202012 May 23

Other

Other2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
CountryKorea, Republic of
CitySeoul
Period12-05-2012-05-23

Fingerprint

Mixer circuits
Zigbee
Low noise amplifiers
Electric power utilization
Thermal noise
Bias currents
Noise figure
Specifications
Networks (circuits)
Electric potential

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Lee, S-Y., Wang, L. H., Chen, T. Y., & Yu, C. T. (2012). A low-power RF front-end with merged LNA, differential power splitter, and quadrature mixer for IEEE 802.15.4 (ZigBee) applications. 1492-1495. Paper presented at 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of. https://doi.org/10.1109/ISCAS.2012.6271531
Lee, Shuenn-Yuh ; Wang, Liang Hung ; Chen, Tsung Yen ; Yu, Chih Tao. / A low-power RF front-end with merged LNA, differential power splitter, and quadrature mixer for IEEE 802.15.4 (ZigBee) applications. Paper presented at 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of.4 p.
@conference{7402fd05b969421aa0d0e7bcc2188aa3,
title = "A low-power RF front-end with merged LNA, differential power splitter, and quadrature mixer for IEEE 802.15.4 (ZigBee) applications",
abstract = "A 2.4 GHz fully integrated CMOS RF front-end with low-noise amplifier (LNA), differential power splitter (DPS), and quadrature mixer based on current-reused folded architecture is proposed. The circuit has been implemented to fit the specifications of IEEE 802.15.4 2.4 GHz standard. To address the low power consumption issue, the active differential power splitter is directly stacked upon the LNA to allow the reuse of the DC bias current. The folded structure is implemented by using the PMOS device as the quadrature mixer to achieve low flicker and thermal noise, simultaneously. Both the LNA and the DPS are biased in the subthreshold region, which can offer superior gain per current consumption as compared with operation in the strong-inversion region. The chip is fabricated in the 0.18 μm CMOS process with an area of 1.69 mm 2 at a supply voltage of 1.2 V and power consumption of 1.08 mW. Based on the measurement results, the conversion gain of 20.5 dB and S11 of 17 dB can be obtained, respectively. Moreover, the IIP3 in the whole chip is 7.8 dBm, and the total double-side band noise figure is 13.2 dB.",
author = "Shuenn-Yuh Lee and Wang, {Liang Hung} and Chen, {Tsung Yen} and Yu, {Chih Tao}",
year = "2012",
month = "9",
day = "28",
doi = "10.1109/ISCAS.2012.6271531",
language = "English",
pages = "1492--1495",
note = "2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 ; Conference date: 20-05-2012 Through 23-05-2012",

}

Lee, S-Y, Wang, LH, Chen, TY & Yu, CT 2012, 'A low-power RF front-end with merged LNA, differential power splitter, and quadrature mixer for IEEE 802.15.4 (ZigBee) applications', Paper presented at 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of, 12-05-20 - 12-05-23 pp. 1492-1495. https://doi.org/10.1109/ISCAS.2012.6271531

A low-power RF front-end with merged LNA, differential power splitter, and quadrature mixer for IEEE 802.15.4 (ZigBee) applications. / Lee, Shuenn-Yuh; Wang, Liang Hung; Chen, Tsung Yen; Yu, Chih Tao.

2012. 1492-1495 Paper presented at 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of.

Research output: Contribution to conferencePaper

TY - CONF

T1 - A low-power RF front-end with merged LNA, differential power splitter, and quadrature mixer for IEEE 802.15.4 (ZigBee) applications

AU - Lee, Shuenn-Yuh

AU - Wang, Liang Hung

AU - Chen, Tsung Yen

AU - Yu, Chih Tao

PY - 2012/9/28

Y1 - 2012/9/28

N2 - A 2.4 GHz fully integrated CMOS RF front-end with low-noise amplifier (LNA), differential power splitter (DPS), and quadrature mixer based on current-reused folded architecture is proposed. The circuit has been implemented to fit the specifications of IEEE 802.15.4 2.4 GHz standard. To address the low power consumption issue, the active differential power splitter is directly stacked upon the LNA to allow the reuse of the DC bias current. The folded structure is implemented by using the PMOS device as the quadrature mixer to achieve low flicker and thermal noise, simultaneously. Both the LNA and the DPS are biased in the subthreshold region, which can offer superior gain per current consumption as compared with operation in the strong-inversion region. The chip is fabricated in the 0.18 μm CMOS process with an area of 1.69 mm 2 at a supply voltage of 1.2 V and power consumption of 1.08 mW. Based on the measurement results, the conversion gain of 20.5 dB and S11 of 17 dB can be obtained, respectively. Moreover, the IIP3 in the whole chip is 7.8 dBm, and the total double-side band noise figure is 13.2 dB.

AB - A 2.4 GHz fully integrated CMOS RF front-end with low-noise amplifier (LNA), differential power splitter (DPS), and quadrature mixer based on current-reused folded architecture is proposed. The circuit has been implemented to fit the specifications of IEEE 802.15.4 2.4 GHz standard. To address the low power consumption issue, the active differential power splitter is directly stacked upon the LNA to allow the reuse of the DC bias current. The folded structure is implemented by using the PMOS device as the quadrature mixer to achieve low flicker and thermal noise, simultaneously. Both the LNA and the DPS are biased in the subthreshold region, which can offer superior gain per current consumption as compared with operation in the strong-inversion region. The chip is fabricated in the 0.18 μm CMOS process with an area of 1.69 mm 2 at a supply voltage of 1.2 V and power consumption of 1.08 mW. Based on the measurement results, the conversion gain of 20.5 dB and S11 of 17 dB can be obtained, respectively. Moreover, the IIP3 in the whole chip is 7.8 dBm, and the total double-side band noise figure is 13.2 dB.

UR - http://www.scopus.com/inward/record.url?scp=84866605242&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84866605242&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2012.6271531

DO - 10.1109/ISCAS.2012.6271531

M3 - Paper

AN - SCOPUS:84866605242

SP - 1492

EP - 1495

ER -

Lee S-Y, Wang LH, Chen TY, Yu CT. A low-power RF front-end with merged LNA, differential power splitter, and quadrature mixer for IEEE 802.15.4 (ZigBee) applications. 2012. Paper presented at 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of. https://doi.org/10.1109/ISCAS.2012.6271531