A low power synthesis flow for multi-rate systems

Hsin Pang Kuo, Alan P. Su, Kuen-Jong Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper we develop a synthesis flow for multi-rate systems modelled by SDF graphs with the objective of minimizing power consumption while satisfying the given throughput constraint and using as few asynchronous FIFOs as possible. A novel hybrid synchronous/asynchronous buffering mechanism to optimize computation power using self-timed scheduling and Globally Asynchronous Locally Synchronous (GALS) architecture is proposed. This hybrid buffering mechanism employs a just-enough size of buffers for data synchronization in the computational components and then inserts the minimal size of asynchronous FIFOs for the Clock-Domain-Crossing (CDC) communication. Experimental results on a JPEG encoder show that 82.7% power reduction is achieved compared to the single clock domain design, and 53.9% power reduction compared to the generic GALS design without the proposed hybrid buffering mechanism.

Original languageEnglish
Title of host publication2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509039692
DOIs
Publication statusPublished - 2017 Jun 5
Event2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 - Hsinchu, Taiwan
Duration: 2017 Apr 242017 Apr 27

Other

Other2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
CountryTaiwan
CityHsinchu
Period17-04-2417-04-27

Fingerprint

Clocks
Synchronization
Electric power utilization
Scheduling
Throughput
Communication

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Kuo, H. P., Su, A. P., & Lee, K-J. (2017). A low power synthesis flow for multi-rate systems. In 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 [7939677] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2017.7939677
Kuo, Hsin Pang ; Su, Alan P. ; Lee, Kuen-Jong. / A low power synthesis flow for multi-rate systems. 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017. Institute of Electrical and Electronics Engineers Inc., 2017.
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title = "A low power synthesis flow for multi-rate systems",
abstract = "In this paper we develop a synthesis flow for multi-rate systems modelled by SDF graphs with the objective of minimizing power consumption while satisfying the given throughput constraint and using as few asynchronous FIFOs as possible. A novel hybrid synchronous/asynchronous buffering mechanism to optimize computation power using self-timed scheduling and Globally Asynchronous Locally Synchronous (GALS) architecture is proposed. This hybrid buffering mechanism employs a just-enough size of buffers for data synchronization in the computational components and then inserts the minimal size of asynchronous FIFOs for the Clock-Domain-Crossing (CDC) communication. Experimental results on a JPEG encoder show that 82.7{\%} power reduction is achieved compared to the single clock domain design, and 53.9{\%} power reduction compared to the generic GALS design without the proposed hybrid buffering mechanism.",
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Kuo, HP, Su, AP & Lee, K-J 2017, A low power synthesis flow for multi-rate systems. in 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017., 7939677, Institute of Electrical and Electronics Engineers Inc., 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017, Hsinchu, Taiwan, 17-04-24. https://doi.org/10.1109/VLSI-DAT.2017.7939677

A low power synthesis flow for multi-rate systems. / Kuo, Hsin Pang; Su, Alan P.; Lee, Kuen-Jong.

2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017. Institute of Electrical and Electronics Engineers Inc., 2017. 7939677.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AB - In this paper we develop a synthesis flow for multi-rate systems modelled by SDF graphs with the objective of minimizing power consumption while satisfying the given throughput constraint and using as few asynchronous FIFOs as possible. A novel hybrid synchronous/asynchronous buffering mechanism to optimize computation power using self-timed scheduling and Globally Asynchronous Locally Synchronous (GALS) architecture is proposed. This hybrid buffering mechanism employs a just-enough size of buffers for data synchronization in the computational components and then inserts the minimal size of asynchronous FIFOs for the Clock-Domain-Crossing (CDC) communication. Experimental results on a JPEG encoder show that 82.7% power reduction is achieved compared to the single clock domain design, and 53.9% power reduction compared to the generic GALS design without the proposed hybrid buffering mechanism.

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Kuo HP, Su AP, Lee K-J. A low power synthesis flow for multi-rate systems. In 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017. Institute of Electrical and Electronics Engineers Inc. 2017. 7939677 https://doi.org/10.1109/VLSI-DAT.2017.7939677