Abstract
In this paper we develop a synthesis flow for multi-rate systems modelled by SDF graphs with the objective of minimizing power consumption while satisfying the given throughput constraint and using as few asynchronous FIFOs as possible. A novel hybrid synchronous/asynchronous buffering mechanism to optimize computation power using self-timed scheduling and Globally Asynchronous Locally Synchronous (GALS) architecture is proposed. This hybrid buffering mechanism employs a just-enough size of buffers for data synchronization in the computational components and then inserts the minimal size of asynchronous FIFOs for the Clock-Domain-Crossing (CDC) communication. Experimental results on a JPEG encoder show that 82.7% power reduction is achieved compared to the single clock domain design, and 53.9% power reduction compared to the generic GALS design without the proposed hybrid buffering mechanism.
Original language | English |
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Title of host publication | 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781509039692 |
DOIs | |
Publication status | Published - 2017 Jun 5 |
Event | 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 - Hsinchu, Taiwan Duration: 2017 Apr 24 → 2017 Apr 27 |
Other
Other | 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 |
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Country/Territory | Taiwan |
City | Hsinchu |
Period | 17-04-24 → 17-04-27 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality