A low power synthesis flow for multi-rate systems

Hsin Pang Kuo; Alan P. Su; Kuen-Jong Lee

doi:10.1109/VLSI-DAT.2017.7939677

A low power synthesis flow for multi-rate systems

Hsin Pang Kuo, Alan P. Su, Kuen-Jong Lee

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

In this paper we develop a synthesis flow for multi-rate systems modelled by SDF graphs with the objective of minimizing power consumption while satisfying the given throughput constraint and using as few asynchronous FIFOs as possible. A novel hybrid synchronous/asynchronous buffering mechanism to optimize computation power using self-timed scheduling and Globally Asynchronous Locally Synchronous (GALS) architecture is proposed. This hybrid buffering mechanism employs a just-enough size of buffers for data synchronization in the computational components and then inserts the minimal size of asynchronous FIFOs for the Clock-Domain-Crossing (CDC) communication. Experimental results on a JPEG encoder show that 82.7% power reduction is achieved compared to the single clock domain design, and 53.9% power reduction compared to the generic GALS design without the proposed hybrid buffering mechanism.

Original language	English
Title of host publication	2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509039692
DOIs	https://doi.org/10.1109/VLSI-DAT.2017.7939677
Publication status	Published - 2017 Jun 5
Event	2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 - Hsinchu, Taiwan Duration: 2017 Apr 24 → 2017 Apr 27

Other

Other	2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
Country/Territory	Taiwan
City	Hsinchu
Period	17-04-24 → 17-04-27

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

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10.1109/VLSI-DAT.2017.7939677

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@inproceedings{11ac4d9288a944f39dcab96f4dd67438,

title = "A low power synthesis flow for multi-rate systems",

abstract = "In this paper we develop a synthesis flow for multi-rate systems modelled by SDF graphs with the objective of minimizing power consumption while satisfying the given throughput constraint and using as few asynchronous FIFOs as possible. A novel hybrid synchronous/asynchronous buffering mechanism to optimize computation power using self-timed scheduling and Globally Asynchronous Locally Synchronous (GALS) architecture is proposed. This hybrid buffering mechanism employs a just-enough size of buffers for data synchronization in the computational components and then inserts the minimal size of asynchronous FIFOs for the Clock-Domain-Crossing (CDC) communication. Experimental results on a JPEG encoder show that 82.7% power reduction is achieved compared to the single clock domain design, and 53.9% power reduction compared to the generic GALS design without the proposed hybrid buffering mechanism.",

author = "Kuo, {Hsin Pang} and Su, {Alan P.} and Kuen-Jong Lee",

year = "2017",

month = jun,

day = "5",

doi = "10.1109/VLSI-DAT.2017.7939677",

language = "English",

booktitle = "2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 ; Conference date: 24-04-2017 Through 27-04-2017",

}

Kuo, HP, Su, AP & Lee, K-J 2017, A low power synthesis flow for multi-rate systems. in 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017., 7939677, Institute of Electrical and Electronics Engineers Inc., 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017, Hsinchu, Taiwan, 17-04-24. https://doi.org/10.1109/VLSI-DAT.2017.7939677

TY - GEN

T1 - A low power synthesis flow for multi-rate systems

AU - Kuo, Hsin Pang

AU - Su, Alan P.

AU - Lee, Kuen-Jong

PY - 2017/6/5

Y1 - 2017/6/5

N2 - In this paper we develop a synthesis flow for multi-rate systems modelled by SDF graphs with the objective of minimizing power consumption while satisfying the given throughput constraint and using as few asynchronous FIFOs as possible. A novel hybrid synchronous/asynchronous buffering mechanism to optimize computation power using self-timed scheduling and Globally Asynchronous Locally Synchronous (GALS) architecture is proposed. This hybrid buffering mechanism employs a just-enough size of buffers for data synchronization in the computational components and then inserts the minimal size of asynchronous FIFOs for the Clock-Domain-Crossing (CDC) communication. Experimental results on a JPEG encoder show that 82.7% power reduction is achieved compared to the single clock domain design, and 53.9% power reduction compared to the generic GALS design without the proposed hybrid buffering mechanism.

AB - In this paper we develop a synthesis flow for multi-rate systems modelled by SDF graphs with the objective of minimizing power consumption while satisfying the given throughput constraint and using as few asynchronous FIFOs as possible. A novel hybrid synchronous/asynchronous buffering mechanism to optimize computation power using self-timed scheduling and Globally Asynchronous Locally Synchronous (GALS) architecture is proposed. This hybrid buffering mechanism employs a just-enough size of buffers for data synchronization in the computational components and then inserts the minimal size of asynchronous FIFOs for the Clock-Domain-Crossing (CDC) communication. Experimental results on a JPEG encoder show that 82.7% power reduction is achieved compared to the single clock domain design, and 53.9% power reduction compared to the generic GALS design without the proposed hybrid buffering mechanism.

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DO - 10.1109/VLSI-DAT.2017.7939677

M3 - Conference contribution

AN - SCOPUS:85021412428

BT - 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017

Y2 - 24 April 2017 through 27 April 2017

ER -

A low power synthesis flow for multi-rate systems

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