A low-spurious low-power 12-bit 300MS/s DAC with 0.1mm2 in 0.18μm CMOS process

Wei Te Lin, Tai Haur Kuo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A low-spurious low-power 12-bit 300MS/s digital-to-analog converter (DAC) is proposed with only 0.1mm2 active area in a 0.18μm CMOS process. Measured performance achieves > 70dB spurious-free dynamic range (SFDR) in the whole Nyquist bandwidth and consumes 35mW. Two popular figure-of-merits (FoMs) are used to compare this design with other published DACs, with the proposed design performing best.

Original languageEnglish
Title of host publication2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013
DOIs
Publication statusPublished - 2013 Dec 23
Event2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 - Hong Kong, Hong Kong
Duration: 2013 Jun 32013 Jun 5

Publication series

Name2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013

Other

Other2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013
CountryHong Kong
CityHong Kong
Period13-06-0313-06-05

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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