A memory built-in self-diagnosis design with syndrome compression

Rei Fu Huang, Chin Lung Su, Cheng Wen Wu, Yeong Jar Chang, Wen Ching Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

We present a memory built-in self-diagnosis (BISD) design that incorporates a fault syndrome compression scheme. We also have developed efficient faulty-word, faulty-row, and faulty-column identification methods, which have been incorporated in our new BISD design. Our approach reduces the amount of data that need to be transmitted from the chip under test to the automatic test equipment (ATE). It therefore reduces the ATE occupation time and the required ATE capture memory space. It also simplifies the analysis that has to be performed on the ATE. Simulation results for memories under various fault pattern distributions show that in most cases the data can be compressed to less than 6% of its original size.

Original languageEnglish
Title of host publicationProceedings - 2004 IEEE International Workshop on Current and Defect Based Testing, DBT 2004
EditorsS. Menon, J. Plusquellic, A. Singh, H. Manhaeve
Pages99-104
Number of pages6
Publication statusPublished - 2004 Dec 1
Event2004 IEEE International Workshop on Current and Defect Based Testing, DBT 2004 - Napa Valley, CA, United States
Duration: 2004 Apr 252004 Apr 25

Publication series

NameProceedings - 2004 IEEE International Workshop on Current and Defect Based Testing, DBT 2004

Conference

Conference2004 IEEE International Workshop on Current and Defect Based Testing, DBT 2004
CountryUnited States
CityNapa Valley, CA
Period04-04-2504-04-25

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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