TY - GEN
T1 - A memory efficient architecture for deblocking filter in H.264 using vertical processing order
AU - Chen, Chung Ming
AU - Chen, Chung-Ho
PY - 2005/12/1
Y1 - 2005/12/1
N2 - In this paper, we study and analyze the memory reference of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference is known to be very time consuming in this new video coding standard. In order to reduce the memory reference and thus improve overall system performance, we propose a vertical processing order with efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the memory performance of the proposed architecture is improved by 4.4 times when compared to software implementation. Moreover, the system performance of our proposal is 129% faster than the advanced architecture of previous proposal.
AB - In this paper, we study and analyze the memory reference of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference is known to be very time consuming in this new video coding standard. In order to reduce the memory reference and thus improve overall system performance, we propose a vertical processing order with efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the memory performance of the proposed architecture is improved by 4.4 times when compared to software implementation. Moreover, the system performance of our proposal is 129% faster than the advanced architecture of previous proposal.
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M3 - Conference contribution
AN - SCOPUS:33847179855
SN - 0780393996
SN - 9780780393998
T3 - Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference
SP - 361
EP - 366
BT - Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference
T2 - 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference
Y2 - 5 December 2005 through 8 December 2005
ER -