A memory efficient architecture for deblocking filter in H.264 using vertical processing order

Chung Ming Chen; Chung-Ho Chen

A memory efficient architecture for deblocking filter in H.264 using vertical processing order

Chung Ming Chen, Chung-Ho Chen

Institute of Computer and Communication Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

15 Citations (Scopus)

Abstract

In this paper, we study and analyze the memory reference of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference is known to be very time consuming in this new video coding standard. In order to reduce the memory reference and thus improve overall system performance, we propose a vertical processing order with efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the memory performance of the proposed architecture is improved by 4.4 times when compared to software implementation. Moreover, the system performance of our proposal is 129% faster than the advanced architecture of previous proposal.

Original language	English
Title of host publication	Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference
Pages	361-366
Number of pages	6
Publication status	Published - 2005 Dec 1
Event	2005 Intelligent Sensors, Sensor Networks and Information Processing Conference - Melbourne, Australia Duration: 2005 Dec 5 → 2005 Dec 8

Publication series

Name	Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference
Volume	2005

Other

Other	2005 Intelligent Sensors, Sensor Networks and Information Processing Conference
Country	Australia
City	Melbourne
Period	05-12-05 → 05-12-08

All Science Journal Classification (ASJC) codes

Engineering(all)

Fingerprint Dive into the research topics of 'A memory efficient architecture for deblocking filter in H.264 using vertical processing order'. Together they form a unique fingerprint.

Cite this

@inproceedings{6ee398556d0a4890aca799073468a719,

title = "A memory efficient architecture for deblocking filter in H.264 using vertical processing order",

abstract = "In this paper, we study and analyze the memory reference of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference is known to be very time consuming in this new video coding standard. In order to reduce the memory reference and thus improve overall system performance, we propose a vertical processing order with efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the memory performance of the proposed architecture is improved by 4.4 times when compared to software implementation. Moreover, the system performance of our proposal is 129% faster than the advanced architecture of previous proposal.",

author = "Chen, {Chung Ming} and Chung-Ho Chen",

year = "2005",

month = dec,

day = "1",

language = "English",

isbn = "0780393996",

series = "Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference",

pages = "361--366",

booktitle = "Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference",

note = "2005 Intelligent Sensors, Sensor Networks and Information Processing Conference ; Conference date: 05-12-2005 Through 08-12-2005",

}

Chen, CM & Chen, C-H 2005, A memory efficient architecture for deblocking filter in H.264 using vertical processing order. in Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference., 1595606, Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference, vol. 2005, pp. 361-366, 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference, Melbourne, Australia, 05-12-05.

A memory efficient architecture for deblocking filter in H.264 using vertical processing order. / Chen, Chung Ming; Chen, Chung-Ho.

Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference. 2005. p. 361-366 1595606 (Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A memory efficient architecture for deblocking filter in H.264 using vertical processing order

AU - Chen, Chung Ming

AU - Chen, Chung-Ho

PY - 2005/12/1

Y1 - 2005/12/1

N2 - In this paper, we study and analyze the memory reference of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference is known to be very time consuming in this new video coding standard. In order to reduce the memory reference and thus improve overall system performance, we propose a vertical processing order with efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the memory performance of the proposed architecture is improved by 4.4 times when compared to software implementation. Moreover, the system performance of our proposal is 129% faster than the advanced architecture of previous proposal.

AB - In this paper, we study and analyze the memory reference of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference is known to be very time consuming in this new video coding standard. In order to reduce the memory reference and thus improve overall system performance, we propose a vertical processing order with efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the memory performance of the proposed architecture is improved by 4.4 times when compared to software implementation. Moreover, the system performance of our proposal is 129% faster than the advanced architecture of previous proposal.

UR - http://www.scopus.com/inward/record.url?scp=33847179855&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33847179855&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:33847179855

SN - 0780393996

SN - 9780780393998

T3 - Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference

SP - 361

EP - 366

BT - Proceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference

T2 - 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference

Y2 - 5 December 2005 through 8 December 2005

ER -