A memory efficient architecture for deblocking filter in H.264 using vertical processing order

Chung Ming Chen, Chung-Ho Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Abstract

In this paper, we study and analyze the memory reference of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference is known to be very time consuming in this new video coding standard. In order to reduce the memory reference and thus improve overall system performance, we propose a vertical processing order with efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the memory performance of the proposed architecture is improved by 4.4 times when compared to software implementation. Moreover, the system performance of our proposal is 129% faster than the advanced architecture of previous proposal.

Original languageEnglish
Title of host publicationProceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference
Pages361-366
Number of pages6
Publication statusPublished - 2005 Dec 1
Event2005 Intelligent Sensors, Sensor Networks and Information Processing Conference - Melbourne, Australia
Duration: 2005 Dec 52005 Dec 8

Publication series

NameProceedings of the 2005 Intelligent Sensors, Sensor Networks and Information Processing Conference
Volume2005

Other

Other2005 Intelligent Sensors, Sensor Networks and Information Processing Conference
CountryAustralia
CityMelbourne
Period05-12-0505-12-08

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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