A memory-efficient NoC system for OpenCL many-core platform

Chien Hsuan Yen; Chung Ho Chen; Kuan Chung Chen

doi:10.1109/ISCAS.2015.7168901

A memory-efficient NoC system for OpenCL many-core platform

Chien Hsuan Yen, Chung Ho Chen, Kuan Chung Chen

Institute of Computer and Communication Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

We present a memory-efficient NoC system for OpenCL many-core platforms. By offloading the OpenCL kernel programs into the many-core processor, we reveal that the memory contention overheads have dramatically increased with the scaling of the system, resulting to the poor performance scalability of the many-core system. We explore a memory-efficient NoC system design which includes a mesh network, a hybrid network interface for packet composition and decomposition, and a memory controller with access scheduling capability. Our experimental results show that a simple memory access scheduling and caching approach can easily boost the performance of the NoC and memory system up to 20 percent by eliminating the memory controller contention problem.

Original language	English
Title of host publication	2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1386-1389
Number of pages	4
ISBN (Electronic)	9781479983919
DOIs	https://doi.org/10.1109/ISCAS.2015.7168901
Publication status	Published - 2015 Jul 27
Event	IEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal Duration: 2015 May 24 → 2015 May 27

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2015-July
ISSN (Print)	0271-4310

Other

Other	IEEE International Symposium on Circuits and Systems, ISCAS 2015
Country	Portugal
City	Lisbon
Period	15-05-24 → 15-05-27

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2015.7168901

Fingerprint Dive into the research topics of 'A memory-efficient NoC system for OpenCL many-core platform'. Together they form a unique fingerprint.

Cite this

Yen, C. H., Chen, C. H., & Chen, K. C. (2015). A memory-efficient NoC system for OpenCL many-core platform. In 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015 (pp. 1386-1389). [7168901] (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2015-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2015.7168901

@inproceedings{c990c5d04bcc48829c97a99ed8e94771,

title = "A memory-efficient NoC system for OpenCL many-core platform",

abstract = "We present a memory-efficient NoC system for OpenCL many-core platforms. By offloading the OpenCL kernel programs into the many-core processor, we reveal that the memory contention overheads have dramatically increased with the scaling of the system, resulting to the poor performance scalability of the many-core system. We explore a memory-efficient NoC system design which includes a mesh network, a hybrid network interface for packet composition and decomposition, and a memory controller with access scheduling capability. Our experimental results show that a simple memory access scheduling and caching approach can easily boost the performance of the NoC and memory system up to 20 percent by eliminating the memory controller contention problem.",

author = "Yen, {Chien Hsuan} and Chen, {Chung Ho} and Chen, {Kuan Chung}",

year = "2015",

month = jul,

day = "27",

doi = "10.1109/ISCAS.2015.7168901",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1386--1389",

booktitle = "2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015",

address = "United States",

note = "IEEE International Symposium on Circuits and Systems, ISCAS 2015 ; Conference date: 24-05-2015 Through 27-05-2015",

}

Yen, CH, Chen, CH & Chen, KC 2015, A memory-efficient NoC system for OpenCL many-core platform. in 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015., 7168901, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2015-July, Institute of Electrical and Electronics Engineers Inc., pp. 1386-1389, IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, 15-05-24. https://doi.org/10.1109/ISCAS.2015.7168901

A memory-efficient NoC system for OpenCL many-core platform. / Yen, Chien Hsuan; Chen, Chung Ho; Chen, Kuan Chung.

2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 1386-1389 7168901 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2015-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A memory-efficient NoC system for OpenCL many-core platform

AU - Yen, Chien Hsuan

AU - Chen, Chung Ho

AU - Chen, Kuan Chung

PY - 2015/7/27

Y1 - 2015/7/27

N2 - We present a memory-efficient NoC system for OpenCL many-core platforms. By offloading the OpenCL kernel programs into the many-core processor, we reveal that the memory contention overheads have dramatically increased with the scaling of the system, resulting to the poor performance scalability of the many-core system. We explore a memory-efficient NoC system design which includes a mesh network, a hybrid network interface for packet composition and decomposition, and a memory controller with access scheduling capability. Our experimental results show that a simple memory access scheduling and caching approach can easily boost the performance of the NoC and memory system up to 20 percent by eliminating the memory controller contention problem.

AB - We present a memory-efficient NoC system for OpenCL many-core platforms. By offloading the OpenCL kernel programs into the many-core processor, we reveal that the memory contention overheads have dramatically increased with the scaling of the system, resulting to the poor performance scalability of the many-core system. We explore a memory-efficient NoC system design which includes a mesh network, a hybrid network interface for packet composition and decomposition, and a memory controller with access scheduling capability. Our experimental results show that a simple memory access scheduling and caching approach can easily boost the performance of the NoC and memory system up to 20 percent by eliminating the memory controller contention problem.

UR - http://www.scopus.com/inward/record.url?scp=84946236397&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84946236397&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2015.7168901

DO - 10.1109/ISCAS.2015.7168901

M3 - Conference contribution

AN - SCOPUS:84946236397

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 1386

EP - 1389

BT - 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International Symposium on Circuits and Systems, ISCAS 2015

Y2 - 24 May 2015 through 27 May 2015

ER -