A memory-efficient TCAM COPROCESSOR for IPv4/IPv6 routing table update

Fang Chen Kuo, Yeim Kuan Chang, Cheng Chien Su

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

Ternary content-addressable memory (TCAM) is a simple hardware device for fast IP lookups that can perform a lookup per cycle. However, prefixes may be inserted into or deleted from the TCAM because of changes in Internet topology. Traditional TCAM coprocessors maintain the enclosure relationship among prefixes by using an extended binary trie and perform TCAM movements based on an update algorithm (e.g., CAO-OPT) which runs on a local CPU to maintain the speed and correctness of the TCAM search process. In this paper, we propose a memory-efficient TCAM coprocessor architecture for updates that require only small memory size compared with the extended binary trie. The average number of TCAM movements per update is almost the same as that of CAO-OPT. However, the time to compute how to move TCAM entries in the proposed TCAM coprocessor is less than that in CAO-OPT. Only a small part of total TCAM search cycles is used to complete our update process. The proposed TCAM architecture can also be made smaller and faster because large off-chip memory for the extended binary trie and a local CPU are no longer necessary.

Original languageEnglish
Article number6422297
Pages (from-to)2110-2121
Number of pages12
JournalIEEE Transactions on Computers
Volume63
Issue number9
DOIs
Publication statusPublished - 2014 Sep 1

All Science Journal Classification (ASJC) codes

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

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