A memory failure pattern analyzer for memory diagnosis and repair

Bing Yang Lin, Mincent Lee, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)


As VLSI technology advances and memories occupy more and more area in a typical SOC, memory diagnosis has become an important issue. In this paper, we propose the Memory Failure Pattern Analyzer (MFPA), which is developed for different memories and technologies that are currently used in the industry. The MFPA can locate weak regions of the memory array, i.e., those with high failure rate. It can also be used to analyze faulty-cell/defect distributions automatically. We also propose a new defect distribution model which has 1-12 times higher accuracy than other theoretical models. Based on this model, we propose a defect-spectrum-based methodology to identify critical failure patterns from failure bitmaps. These failure patterns can further be translated to corresponding defects by our memory fault simulator (RAMSES) and physical-level failure analysis tool (FAME). In an industrial case, the MFPA fits the defect distribution with the proposed model, which has 12 times higher accuracy than the Poisson distribution. With our model, it further identifies two special failure patterns from 132,488 faulty 4-Mb macros in 1.2 minutes.

Original languageEnglish
Title of host publicationProceedings - 2012 30th IEEE VLSI Test Symposium, VTS 2012
Number of pages6
Publication statusPublished - 2012 Aug 20
Event2012 30th IEEE VLSI Test Symposium, VTS 2012 - Hyatt Maui, HI, United States
Duration: 2012 Apr 232012 Apr 26

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Conference2012 30th IEEE VLSI Test Symposium, VTS 2012
Country/TerritoryUnited States
CityHyatt Maui, HI

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering


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