A network security processor design based on an integrated SOC design and test platform

Chen Hsing Wang, Chih Yen Lo, Min Sheng Lee, Jen Chieh Yeh, Chih Tsun Huang, Cheng Wen Wu, Shi Yu Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)


In this paper we present a generic Network Security Processor (NSP) design suitable for a wide range of security related protocols in wired or wireless network applications.Following the platform-based design methodology, we develop four specific platforms, i.e., architecture platform, EDA platform, Design-for-Testability (DFT) platform, and prototyping platform, for our NSP design.With these platforms, design of the NSP chip becomes more efficient and systematic.A prototype chip of the NSP has been implemented and fabricated with a 0.18m CMOS technology.The chip area is 5mmx5mm (with 1M gates approximately), including I/O pads.The operating clock rate is 80MHz.The best performance of the crypto-engines is 1.025Gbps for AES, 1.652Mbps for RSA, 125.9/157.65Mbps for HMAC-SHA1/MD5, and 2.56Gbps for random number generator.Comparison result shows that our NSP is efficient in terms of performance, flexibility and scalability.

Original languageEnglish
Title of host publication2006 43rd ACM/IEEE Design Automation Conference, DAC'06
Number of pages6
Publication statusPublished - 2006 Dec 1

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering

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