TY - JOUR
T1 - A new compact low-offset push-pull output buffer with current positive feedback for a 10-bit LCD source driver
AU - Tsai, Chien-Hung
AU - Wang, J. H.
AU - Zheng, H. Y.
AU - Chang, C. T.
AU - Wang, C. Y.
PY - 2010/11/1
Y1 - 2010/11/1
N2 - In this study, a low-offset push-pull output buffer and an area-efficient resistor-capacitor digital-to-analogue converter for a 10-bit liquid crystal display (LCD) source driver are presented. Compared to other push-pull output buffers, the proposed output buffer has a smaller area and lower power consumption. Two complementary push-pull output buffers driving a pair of column lines realise a rail-to-rail driver. The output buffer has strong driving capability with push-pull function by the current positive feedback (CPF). Therefore the source driver can drive the pixel with two-dot inversion to decrease power consumption. On the other hand, the proposed output buffer with CPF can integrate the offset average to reduce the offset voltage. The performance is experimentally verified with a prototype chip that occupies a silicon area of 1700×260 μm2 in a 0.35-μm 2P4M CMOS process. The measured settling time is less than 7.8 μs.
AB - In this study, a low-offset push-pull output buffer and an area-efficient resistor-capacitor digital-to-analogue converter for a 10-bit liquid crystal display (LCD) source driver are presented. Compared to other push-pull output buffers, the proposed output buffer has a smaller area and lower power consumption. Two complementary push-pull output buffers driving a pair of column lines realise a rail-to-rail driver. The output buffer has strong driving capability with push-pull function by the current positive feedback (CPF). Therefore the source driver can drive the pixel with two-dot inversion to decrease power consumption. On the other hand, the proposed output buffer with CPF can integrate the offset average to reduce the offset voltage. The performance is experimentally verified with a prototype chip that occupies a silicon area of 1700×260 μm2 in a 0.35-μm 2P4M CMOS process. The measured settling time is less than 7.8 μs.
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U2 - 10.1049/iet-cds.2010.0119
DO - 10.1049/iet-cds.2010.0119
M3 - Article
AN - SCOPUS:78149371227
SN - 1751-858X
VL - 4
SP - 539
EP - 547
JO - IET Circuits, Devices and Systems
JF - IET Circuits, Devices and Systems
IS - 6
ER -