A new design to prevent fault equivalence in PLA's

B. D. Liu, G. T. Shaw

Research output: Contribution to journalConference articlepeer-review

2 Citations (Scopus)

Abstract

The fault equivalence problem in programmable logic arrays (PLAs) is introduced. Some design rules are proposed. Based on the pseudoexhaustive testable PLA structure, a diagnosis algorithm was developed and implemented on a SUN 3/110 workstation in C language. Experimental results show that this design and the algorithm are quite efficient for PLA fault diagnosis.

Original languageEnglish
Pages (from-to)2752-2755
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume4
Publication statusPublished - 1990 Dec 1
Event1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4) - New Orleans, LA, USA
Duration: 1990 May 11990 May 3

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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