A New Device-Parameter-Oriented DC Power Model for Symmetric Operation of Junctionless Double-Gate mosfet Working on Low-Power CMOS Subthreshold Logic Gates

Hong Wun Gao, Yeong-Her Wang, Te Kuang Chiang

Research output: Contribution to journalArticle

Abstract

Based on the subthreshold current and equivalent transistor models, a new device-parameter-oriented average DC power model average DC power (P DC ) for symmetric operation of junctionless double-gate mosfet (JLDGFET) working on the low-power CMOS subthreshold logic gate is developed. Although short-channel effects can increase P DC significantly, the balanced transistor strength will reduce P DC more efficiently by improving the consistency of transistor strength between P-JLDGFET and N-JLDGFET. Being similar to DIBL, the minimum channel length that corresponds to the allowable maximum P DC in designing the low-power logic gate can be determined according to the scaling theory. Although the inverter (INV) may act as the fundamental building unit for the logic circuits due to its least gate counts among INV, nand, and nor, it consumes the most P DC among these logic gates. The minimum DC power P DC ,min can be obtained by tuning the gate work-function, which ensures the equal transistor strength between P-JLDGFET and N-JLDGFET. Both of the variability and sensitivity induced by the process parameters are also accounted for in developing P DC model.

Original languageEnglish
Pages (from-to)424-431
Number of pages8
JournalIEEE Transactions on Nanotechnology
Volume17
Issue number3
DOIs
Publication statusPublished - 2018 May 1

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Logic gates
Transistors
Logic circuits
Tuning

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

Cite this

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title = "A New Device-Parameter-Oriented DC Power Model for Symmetric Operation of Junctionless Double-Gate mosfet Working on Low-Power CMOS Subthreshold Logic Gates",
abstract = "Based on the subthreshold current and equivalent transistor models, a new device-parameter-oriented average DC power model average DC power (P DC ) for symmetric operation of junctionless double-gate mosfet (JLDGFET) working on the low-power CMOS subthreshold logic gate is developed. Although short-channel effects can increase P DC significantly, the balanced transistor strength will reduce P DC more efficiently by improving the consistency of transistor strength between P-JLDGFET and N-JLDGFET. Being similar to DIBL, the minimum channel length that corresponds to the allowable maximum P DC in designing the low-power logic gate can be determined according to the scaling theory. Although the inverter (INV) may act as the fundamental building unit for the logic circuits due to its least gate counts among INV, nand, and nor, it consumes the most P DC among these logic gates. The minimum DC power P DC ,min can be obtained by tuning the gate work-function, which ensures the equal transistor strength between P-JLDGFET and N-JLDGFET. Both of the variability and sensitivity induced by the process parameters are also accounted for in developing P DC model.",
author = "Gao, {Hong Wun} and Yeong-Her Wang and Chiang, {Te Kuang}",
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AU - Gao, Hong Wun

AU - Wang, Yeong-Her

AU - Chiang, Te Kuang

PY - 2018/5/1

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N2 - Based on the subthreshold current and equivalent transistor models, a new device-parameter-oriented average DC power model average DC power (P DC ) for symmetric operation of junctionless double-gate mosfet (JLDGFET) working on the low-power CMOS subthreshold logic gate is developed. Although short-channel effects can increase P DC significantly, the balanced transistor strength will reduce P DC more efficiently by improving the consistency of transistor strength between P-JLDGFET and N-JLDGFET. Being similar to DIBL, the minimum channel length that corresponds to the allowable maximum P DC in designing the low-power logic gate can be determined according to the scaling theory. Although the inverter (INV) may act as the fundamental building unit for the logic circuits due to its least gate counts among INV, nand, and nor, it consumes the most P DC among these logic gates. The minimum DC power P DC ,min can be obtained by tuning the gate work-function, which ensures the equal transistor strength between P-JLDGFET and N-JLDGFET. Both of the variability and sensitivity induced by the process parameters are also accounted for in developing P DC model.

AB - Based on the subthreshold current and equivalent transistor models, a new device-parameter-oriented average DC power model average DC power (P DC ) for symmetric operation of junctionless double-gate mosfet (JLDGFET) working on the low-power CMOS subthreshold logic gate is developed. Although short-channel effects can increase P DC significantly, the balanced transistor strength will reduce P DC more efficiently by improving the consistency of transistor strength between P-JLDGFET and N-JLDGFET. Being similar to DIBL, the minimum channel length that corresponds to the allowable maximum P DC in designing the low-power logic gate can be determined according to the scaling theory. Although the inverter (INV) may act as the fundamental building unit for the logic circuits due to its least gate counts among INV, nand, and nor, it consumes the most P DC among these logic gates. The minimum DC power P DC ,min can be obtained by tuning the gate work-function, which ensures the equal transistor strength between P-JLDGFET and N-JLDGFET. Both of the variability and sensitivity induced by the process parameters are also accounted for in developing P DC model.

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