Based on the subthreshold current and equivalent transistor models, a new device-parameter-oriented average DC power model average DC power (PDC) for symmetric operation of junctionless double-gate mosfet (JLDGFET) working on the low-power CMOS subthreshold logic gate is developed. Although short-channel effects can increase PDC significantly, the balanced transistor strength will reduce PDC more efficiently by improving the consistency of transistor strength between P-JLDGFET and N-JLDGFET. Being similar to DIBL, the minimum channel length that corresponds to the allowable maximum PDC in designing the low-power logic gate can be determined according to the scaling theory. Although the inverter (INV) may act as the fundamental building unit for the logic circuits due to its least gate counts among INV, nand, and nor, it consumes the most PDC among these logic gates. The minimum DC power PDC,min can be obtained by tuning the gate work-function, which ensures the equal transistor strength between P-JLDGFET and N-JLDGFET. Both of the variability and sensitivity induced by the process parameters are also accounted for in developing PDC model.
All Science Journal Classification (ASJC) codes
- Computer Science Applications
- Electrical and Electronic Engineering