### Abstract

Based on the subthreshold current and equivalent transistor models, a new device-parameter-oriented average DC power model average DC power (P
_{DC}
) for symmetric operation of junctionless double-gate mosfet (JLDGFET) working on the low-power CMOS subthreshold logic gate is developed. Although short-channel effects can increase P
_{DC}
significantly, the balanced transistor strength will reduce P
_{DC}
more efficiently by improving the consistency of transistor strength between P-JLDGFET and N-JLDGFET. Being similar to DIBL, the minimum channel length that corresponds to the allowable maximum P
_{DC}
in designing the low-power logic gate can be determined according to the scaling theory. Although the inverter (INV) may act as the fundamental building unit for the logic circuits due to its least gate counts among INV, nand, and nor, it consumes the most P
_{DC}
among these logic gates. The minimum DC power P
_{DC}
,min can be obtained by tuning the gate work-function, which ensures the equal transistor strength between P-JLDGFET and N-JLDGFET. Both of the variability and sensitivity induced by the process parameters are also accounted for in developing P
_{DC}
model.

Original language | English |
---|---|

Pages (from-to) | 424-431 |

Number of pages | 8 |

Journal | IEEE Transactions on Nanotechnology |

Volume | 17 |

Issue number | 3 |

DOIs | |

Publication status | Published - 2018 May 1 |

### Fingerprint

### All Science Journal Classification (ASJC) codes

- Computer Science Applications
- Electrical and Electronic Engineering

### Cite this

*IEEE Transactions on Nanotechnology*,

*17*(3), 424-431. https://doi.org/10.1109/TNANO.2018.2803845

}

*IEEE Transactions on Nanotechnology*, vol. 17, no. 3, pp. 424-431. https://doi.org/10.1109/TNANO.2018.2803845

**A New Device-Parameter-Oriented DC Power Model for Symmetric Operation of Junctionless Double-Gate mosfet Working on Low-Power CMOS Subthreshold Logic Gates.** / Gao, Hong Wun; Wang, Yeong-Her; Chiang, Te Kuang.

Research output: Contribution to journal › Article

TY - JOUR

T1 - A New Device-Parameter-Oriented DC Power Model for Symmetric Operation of Junctionless Double-Gate mosfet Working on Low-Power CMOS Subthreshold Logic Gates

AU - Gao, Hong Wun

AU - Wang, Yeong-Her

AU - Chiang, Te Kuang

PY - 2018/5/1

Y1 - 2018/5/1

N2 - Based on the subthreshold current and equivalent transistor models, a new device-parameter-oriented average DC power model average DC power (P DC ) for symmetric operation of junctionless double-gate mosfet (JLDGFET) working on the low-power CMOS subthreshold logic gate is developed. Although short-channel effects can increase P DC significantly, the balanced transistor strength will reduce P DC more efficiently by improving the consistency of transistor strength between P-JLDGFET and N-JLDGFET. Being similar to DIBL, the minimum channel length that corresponds to the allowable maximum P DC in designing the low-power logic gate can be determined according to the scaling theory. Although the inverter (INV) may act as the fundamental building unit for the logic circuits due to its least gate counts among INV, nand, and nor, it consumes the most P DC among these logic gates. The minimum DC power P DC ,min can be obtained by tuning the gate work-function, which ensures the equal transistor strength between P-JLDGFET and N-JLDGFET. Both of the variability and sensitivity induced by the process parameters are also accounted for in developing P DC model.

AB - Based on the subthreshold current and equivalent transistor models, a new device-parameter-oriented average DC power model average DC power (P DC ) for symmetric operation of junctionless double-gate mosfet (JLDGFET) working on the low-power CMOS subthreshold logic gate is developed. Although short-channel effects can increase P DC significantly, the balanced transistor strength will reduce P DC more efficiently by improving the consistency of transistor strength between P-JLDGFET and N-JLDGFET. Being similar to DIBL, the minimum channel length that corresponds to the allowable maximum P DC in designing the low-power logic gate can be determined according to the scaling theory. Although the inverter (INV) may act as the fundamental building unit for the logic circuits due to its least gate counts among INV, nand, and nor, it consumes the most P DC among these logic gates. The minimum DC power P DC ,min can be obtained by tuning the gate work-function, which ensures the equal transistor strength between P-JLDGFET and N-JLDGFET. Both of the variability and sensitivity induced by the process parameters are also accounted for in developing P DC model.

UR - http://www.scopus.com/inward/record.url?scp=85042073437&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85042073437&partnerID=8YFLogxK

U2 - 10.1109/TNANO.2018.2803845

DO - 10.1109/TNANO.2018.2803845

M3 - Article

AN - SCOPUS:85042073437

VL - 17

SP - 424

EP - 431

JO - IEEE Transactions on Nanotechnology

JF - IEEE Transactions on Nanotechnology

SN - 1536-125X

IS - 3

ER -