A new level converter for low-power applications

Chien Cheng Yu, Wei Ping Wang, Bin-Da Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

29 Citations (Scopus)

Abstract

In dual supply voltage circuits, when connecting a V/sub DDL/-supplied circuit to a V/sub DDH/-supplied circuit, it is necessary to insert a level converter at each low-to-high boundary as the interface to prevent static current. In this paper, we propose a new low-power level converter circuit technique, called Symmetrical Dual Cascode Voltage Switch (SDCVS), which will reduce the contention problem that existed in the conventional Dual Cascode Voltage Switch (DCVS) design. These level converters are simulated for different capacitive loads and operating conditions using the HSPICE parameters of a 0.35 μm digital CMOS technology. The HSPICE simulations show that the proposed circuit can achieve 50% power reduction and 60% speed increase over those of the existing technique. In addition, the proposed level converter can operate at different values of V/sub DDL/ ranging from 1.2 V to 5 V. Hence, the proposed technique is suited for low power design without degrading performance.

Original languageEnglish
Title of host publicationISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Pages113-116
Number of pages4
DOIs
Publication statusPublished - 2001 Dec 1
Event2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia
Duration: 2001 May 62001 May 9

Publication series

NameISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Volume1

Other

Other2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
CountryAustralia
CitySydney, NSW
Period01-05-0601-05-09

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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