TY - GEN
T1 - A new level converter for low-power applications
AU - Yu, Chien Cheng
AU - Wang, Wei Ping
AU - Liu, Bin-Da
PY - 2001/12/1
Y1 - 2001/12/1
N2 - In dual supply voltage circuits, when connecting a V/sub DDL/-supplied circuit to a V/sub DDH/-supplied circuit, it is necessary to insert a level converter at each low-to-high boundary as the interface to prevent static current. In this paper, we propose a new low-power level converter circuit technique, called Symmetrical Dual Cascode Voltage Switch (SDCVS), which will reduce the contention problem that existed in the conventional Dual Cascode Voltage Switch (DCVS) design. These level converters are simulated for different capacitive loads and operating conditions using the HSPICE parameters of a 0.35 μm digital CMOS technology. The HSPICE simulations show that the proposed circuit can achieve 50% power reduction and 60% speed increase over those of the existing technique. In addition, the proposed level converter can operate at different values of V/sub DDL/ ranging from 1.2 V to 5 V. Hence, the proposed technique is suited for low power design without degrading performance.
AB - In dual supply voltage circuits, when connecting a V/sub DDL/-supplied circuit to a V/sub DDH/-supplied circuit, it is necessary to insert a level converter at each low-to-high boundary as the interface to prevent static current. In this paper, we propose a new low-power level converter circuit technique, called Symmetrical Dual Cascode Voltage Switch (SDCVS), which will reduce the contention problem that existed in the conventional Dual Cascode Voltage Switch (DCVS) design. These level converters are simulated for different capacitive loads and operating conditions using the HSPICE parameters of a 0.35 μm digital CMOS technology. The HSPICE simulations show that the proposed circuit can achieve 50% power reduction and 60% speed increase over those of the existing technique. In addition, the proposed level converter can operate at different values of V/sub DDL/ ranging from 1.2 V to 5 V. Hence, the proposed technique is suited for low power design without degrading performance.
UR - http://www.scopus.com/inward/record.url?scp=0035013782&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0035013782&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2001.921801
DO - 10.1109/ISCAS.2001.921801
M3 - Conference contribution
AN - SCOPUS:0035013782
SN - 0780366859
SN - 9780780366855
T3 - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
SP - 113
EP - 116
BT - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
T2 - 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
Y2 - 6 May 2001 through 9 May 2001
ER -