A new design to reduce the overhead required for fully testable programmable logic arrays (PLAs) is proposed. This design exploits the fact that product lines in a PLA can be rearranged and grouped into few partitions. Then, some extra outputs are added, one per partition, to make the whole PLA testable. Compared with the previous PLA design-for-testability techniques, the algorithm presented is very feasible, and its implementation is straightforward. Furthermore, this algorithm significantly lowers overhead and provides substantially higher fault coverage than some existing schemes.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 1991 Dec 1|
|Event||1991 IEEE International Symposium on Circuits and Systems Part 4 (of 5) - Singapore, Singapore|
Duration: 1991 Jun 11 → 1991 Jun 14
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering