A new noise margin and average static power model for junctionless double-gate FETs (JLDGFET) working in subthreshold logic gate

Te Kuang Chiang, Chen Chih Yo, Hong Wun Gao, Yeong-Her Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Based on the device and equivalent transistor models, we present a new device-physics-oriented static noise margin (NM), logic swing, and average power consumption model (Pave) for junctionless double-gate MOSFET (JLDGFET) working on subthreshold CMOS logic gates. Theoretical analysis of the NM and Pave for JLDG MOSFET operating in low-voltage condition is first revealed. The device parameters such as the thick silicon thickness tsi, thick gate oxide thickness tox, large supply voltage Vdd, and short channel length Lg, can severely degrade the NM and induce large Pave due to serious short-channel effect (SCEs). On the contrary, both the small subthreshold slope and balanced transistor strength S induced by device parameters can suppress the NM degradation and reduce Pave efficiently. Being similar to DIBL, both NM and Pave can also be uniquely controlled and determined by the scaling factor according to the scaling theory.

Original languageEnglish
Title of host publication2016 5th International Symposium on Next-Generation Electronics, ISNE 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509024391
DOIs
Publication statusPublished - 2016 Aug 12
Event5th International Symposium on Next-Generation Electronics, ISNE 2016 - Hsinchu, Taiwan
Duration: 2016 May 42016 May 6

Publication series

Name2016 5th International Symposium on Next-Generation Electronics, ISNE 2016

Other

Other5th International Symposium on Next-Generation Electronics, ISNE 2016
CountryTaiwan
CityHsinchu
Period16-05-0416-05-06

Fingerprint

Logic gates
Field effect transistors
Transistors
Electric potential
Silicon
Oxides
Electric power utilization
Physics
Degradation

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Chiang, T. K., Yo, C. C., Gao, H. W., & Wang, Y-H. (2016). A new noise margin and average static power model for junctionless double-gate FETs (JLDGFET) working in subthreshold logic gate. In 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016 [7543300] (2016 5th International Symposium on Next-Generation Electronics, ISNE 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISNE.2016.7543300
Chiang, Te Kuang ; Yo, Chen Chih ; Gao, Hong Wun ; Wang, Yeong-Her. / A new noise margin and average static power model for junctionless double-gate FETs (JLDGFET) working in subthreshold logic gate. 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016. Institute of Electrical and Electronics Engineers Inc., 2016. (2016 5th International Symposium on Next-Generation Electronics, ISNE 2016).
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abstract = "Based on the device and equivalent transistor models, we present a new device-physics-oriented static noise margin (NM), logic swing, and average power consumption model (Pave) for junctionless double-gate MOSFET (JLDGFET) working on subthreshold CMOS logic gates. Theoretical analysis of the NM and Pave for JLDG MOSFET operating in low-voltage condition is first revealed. The device parameters such as the thick silicon thickness tsi, thick gate oxide thickness tox, large supply voltage Vdd, and short channel length Lg, can severely degrade the NM and induce large Pave due to serious short-channel effect (SCEs). On the contrary, both the small subthreshold slope and balanced transistor strength S induced by device parameters can suppress the NM degradation and reduce Pave efficiently. Being similar to DIBL, both NM and Pave can also be uniquely controlled and determined by the scaling factor according to the scaling theory.",
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Chiang, TK, Yo, CC, Gao, HW & Wang, Y-H 2016, A new noise margin and average static power model for junctionless double-gate FETs (JLDGFET) working in subthreshold logic gate. in 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016., 7543300, 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016, Institute of Electrical and Electronics Engineers Inc., 5th International Symposium on Next-Generation Electronics, ISNE 2016, Hsinchu, Taiwan, 16-05-04. https://doi.org/10.1109/ISNE.2016.7543300

A new noise margin and average static power model for junctionless double-gate FETs (JLDGFET) working in subthreshold logic gate. / Chiang, Te Kuang; Yo, Chen Chih; Gao, Hong Wun; Wang, Yeong-Her.

2016 5th International Symposium on Next-Generation Electronics, ISNE 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7543300 (2016 5th International Symposium on Next-Generation Electronics, ISNE 2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - Based on the device and equivalent transistor models, we present a new device-physics-oriented static noise margin (NM), logic swing, and average power consumption model (Pave) for junctionless double-gate MOSFET (JLDGFET) working on subthreshold CMOS logic gates. Theoretical analysis of the NM and Pave for JLDG MOSFET operating in low-voltage condition is first revealed. The device parameters such as the thick silicon thickness tsi, thick gate oxide thickness tox, large supply voltage Vdd, and short channel length Lg, can severely degrade the NM and induce large Pave due to serious short-channel effect (SCEs). On the contrary, both the small subthreshold slope and balanced transistor strength S induced by device parameters can suppress the NM degradation and reduce Pave efficiently. Being similar to DIBL, both NM and Pave can also be uniquely controlled and determined by the scaling factor according to the scaling theory.

AB - Based on the device and equivalent transistor models, we present a new device-physics-oriented static noise margin (NM), logic swing, and average power consumption model (Pave) for junctionless double-gate MOSFET (JLDGFET) working on subthreshold CMOS logic gates. Theoretical analysis of the NM and Pave for JLDG MOSFET operating in low-voltage condition is first revealed. The device parameters such as the thick silicon thickness tsi, thick gate oxide thickness tox, large supply voltage Vdd, and short channel length Lg, can severely degrade the NM and induce large Pave due to serious short-channel effect (SCEs). On the contrary, both the small subthreshold slope and balanced transistor strength S induced by device parameters can suppress the NM degradation and reduce Pave efficiently. Being similar to DIBL, both NM and Pave can also be uniquely controlled and determined by the scaling factor according to the scaling theory.

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Chiang TK, Yo CC, Gao HW, Wang Y-H. A new noise margin and average static power model for junctionless double-gate FETs (JLDGFET) working in subthreshold logic gate. In 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7543300. (2016 5th International Symposium on Next-Generation Electronics, ISNE 2016). https://doi.org/10.1109/ISNE.2016.7543300