A new noise margin and average static power model for junctionless double-gate FETs (JLDGFET) working in subthreshold logic gate

Based on the device and equivalent transistor models, we present a new device-physics-oriented static noise margin (NM), logic swing, and average power consumption model (P_ave) for junctionless double-gate MOSFET (JLDGFET) working on subthreshold CMOS logic gates. Theoretical analysis of the NM and P_ave for JLDG MOSFET operating in low-voltage condition is first revealed. The device parameters such as the thick silicon thickness t_si, thick gate oxide thickness t_ox, large supply voltage V_dd, and short channel length L_g, can severely degrade the NM and induce large P_ave due to serious short-channel effect (SCEs). On the contrary, both the small subthreshold slope and balanced transistor strength S induced by device parameters can suppress the NM degradation and reduce P_ave efficiently. Being similar to DIBL, both NM and P_ave can also be uniquely controlled and determined by the scaling factor according to the scaling theory.