A new pipelined architecture for fuzzy color correction

Jer Min Jou, Shiann Rong Kuang, Yeu Homg Shiau

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Color correction, which nonlinearly converts the color coordinates of an input device such as the scanner into that of an output device such as the printer, is important for multimedia applications. In this paper, we present a novel dynamic pipelined VLSI architecture for the fuzzy color correction algorithm proposed in [1] to meet the speed requirement of time-critical applications. To prompt the performance, the presented architecture is dynamically pipelined with unfixed latencies (or data initiation intervals), then the problem of impossible pipelining (and then slow executing) die fuzzy color correction algorithm due to the variable execution length of each iteration in it is solved completely. As a result, a significant (about 2 times) speed-up of the dynamic pipeline architecture with a slight hardware overhead relative to the sequential architecture has been achieved.

Original languageEnglish
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 1999
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages209-212
Number of pages4
ISBN (Electronic)078035012X
DOIs
Publication statusPublished - 1999
Event4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999 - Wanchai, Hong Kong
Duration: 1999 Jan 181999 Jan 21

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume1999-January

Conference

Conference4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999
Country/TerritoryHong Kong
CityWanchai
Period99-01-1899-01-21

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

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