A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter

M. H. Sheu, H. E. Liao, S. T. Kan, Ming-Der Shieh

Research output: Contribution to journalConference article

Abstract

A novel adaptive algorithm using an IIR narrow band filter (NBPF) is presented to detect a single sinusoid corrupted by Gaussian noise. This algorithm is not only computationally efficient but also suitable for VLSI implementation. The derivation of the adaptive algorithm for frequency begins with an autoregressive (AR) model to formulate a constrained-optimization problem. Then, a new algorithm for frequency detection is derived via the method of Lagrange multiplier. MATLAB simulation shows that our approach has good tracking ability and noise reduction. Finally, a high speed VLSI architecture is designed and implemented according to the proposed algorithm. After hardware simulation, the chip area and clock rate of the whole architecture is 1804×1804um2 and 75MHz respectively by using 0.35um COMS 1P4M technology.

Original languageEnglish
JournalMaterials Research Society Symposium - Proceedings
Volume626
Publication statusPublished - 2001 Jan 1
EventThermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States
Duration: 2000 Apr 242000 Apr 27

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IIR filters
Adaptive filters
very large scale integration
Adaptive algorithms
Lagrange multipliers
Constrained optimization
Noise abatement
MATLAB
Clocks
sine waves
Hardware
random noise
noise reduction
clocks
narrowband
hardware
derivation
simulation
chips
high speed

All Science Journal Classification (ASJC) codes

  • Materials Science(all)
  • Condensed Matter Physics
  • Mechanics of Materials
  • Mechanical Engineering

Cite this

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title = "A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter",
abstract = "A novel adaptive algorithm using an IIR narrow band filter (NBPF) is presented to detect a single sinusoid corrupted by Gaussian noise. This algorithm is not only computationally efficient but also suitable for VLSI implementation. The derivation of the adaptive algorithm for frequency begins with an autoregressive (AR) model to formulate a constrained-optimization problem. Then, a new algorithm for frequency detection is derived via the method of Lagrange multiplier. MATLAB simulation shows that our approach has good tracking ability and noise reduction. Finally, a high speed VLSI architecture is designed and implemented according to the proposed algorithm. After hardware simulation, the chip area and clock rate of the whole architecture is 1804×1804um2 and 75MHz respectively by using 0.35um COMS 1P4M technology.",
author = "Sheu, {M. H.} and Liao, {H. E.} and Kan, {S. T.} and Ming-Der Shieh",
year = "2001",
month = "1",
day = "1",
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A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter. / Sheu, M. H.; Liao, H. E.; Kan, S. T.; Shieh, Ming-Der.

In: Materials Research Society Symposium - Proceedings, Vol. 626, 01.01.2001.

Research output: Contribution to journalConference article

TY - JOUR

T1 - A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter

AU - Sheu, M. H.

AU - Liao, H. E.

AU - Kan, S. T.

AU - Shieh, Ming-Der

PY - 2001/1/1

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N2 - A novel adaptive algorithm using an IIR narrow band filter (NBPF) is presented to detect a single sinusoid corrupted by Gaussian noise. This algorithm is not only computationally efficient but also suitable for VLSI implementation. The derivation of the adaptive algorithm for frequency begins with an autoregressive (AR) model to formulate a constrained-optimization problem. Then, a new algorithm for frequency detection is derived via the method of Lagrange multiplier. MATLAB simulation shows that our approach has good tracking ability and noise reduction. Finally, a high speed VLSI architecture is designed and implemented according to the proposed algorithm. After hardware simulation, the chip area and clock rate of the whole architecture is 1804×1804um2 and 75MHz respectively by using 0.35um COMS 1P4M technology.

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