A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs

T. Yamashita, S. Mehta, V. S. Basker, R. Southwick, A. Kumar, R. Kambhampati, R. Sathiyanarayanan, J. Johnson, T. Hook, S. Cohen, J. Li, A. Madan, Z. Zhu, L. Tai, Y. Yao, P. Chinthamanipeta, M. Hopstaken, Z. Liu, D. Lu, F. ChenS. Khan, D. Canaperi, B. Haran, J. Stathis, P. Oldiges, C. H.C.H. Lin, S. Narasimha, A. Bryant, W. K. Henson, S. Kanakasabapathy, K. V.R.M. Murali, T. Gow, D. McHerron, H. Bu, M. Khare

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)


FinFET has become the mainstream logic device architecture in recent technology nodes due to its superior electrostatic and leakage control [1,2,3,4]. However, parasitic capacitance has been a key performance detractor in 3D FinFETs. In this work, a novel low temperature ALD-based SiBCN material has been identified, with an optimized spacer RIE process developed to preserve the low-k value and provide compatibility with the down-stream processes. The material has been integrated into a manufacturable 14nm replacement-metal-gate (RMG) FinFET baseline with a demonstrated ∼8% performance improvement in the RO delay with reliability meeting the technology requirement [4]. A guideline for spacer design consideration for 10nm node and beyond is also provided based on the comprehensive material properties and reliability evaluations.

Original languageEnglish
Title of host publication2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9784863485013
Publication statusPublished - 2015 Aug 25
EventSymposium on VLSI Technology, VLSI Technology 2015 - Kyoto, Japan
Duration: 2015 Jun 162015 Jun 18

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562


OtherSymposium on VLSI Technology, VLSI Technology 2015

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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