TY - JOUR
T1 - A novel comparison-free 1-D median filter
AU - Lin, Ing Chao
AU - Chen, Wei Ting
AU - Chou, Yu Cheng
AU - Chen, Pei Yin
N1 - Funding Information:
Manuscript received April 30, 2019; revised June 29, 2019 and August 1, 2019; accepted August 11, 2019. Date of publication August 20, 2019; date of current version July 1, 2020. This work was supported in part by the Ministry of Science and Technology of Taiwan under Grant MOST 106-2221-E-006-027-MY3 and Grant 108-2622-8-006-003-TA. This brief was recommended by Associate Editor A. J. Acosta. (Corresponding author: Pei-Yin Chen.) The authors are with the Department of Computer Science and Information Engineering, National Cheng Kung University, Tainan 70101, Taiwan (e-mail: pychen@mail.ncku.edu.tw).
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2020/7
Y1 - 2020/7
N2 - This brief presents a novel high-speed low-cost comparison-free, 1D bit-level median filter. The filter can be customized by cascading different median units. The most prominent point is that a pre-set value is used during the process, and the partial median can be easily identified by observing the MSB. Therefore, the median can be obtained without any comparators. With this feature, the area cost drops significantly while the operating speed remains the same. The results show that when synthesized using TSMC 90nm CMOS process technology, our design can achieve 2000MHz, and the area cost is reduced by 15.72% as compared to a state-of-the-art design.
AB - This brief presents a novel high-speed low-cost comparison-free, 1D bit-level median filter. The filter can be customized by cascading different median units. The most prominent point is that a pre-set value is used during the process, and the partial median can be easily identified by observing the MSB. Therefore, the median can be obtained without any comparators. With this feature, the area cost drops significantly while the operating speed remains the same. The results show that when synthesized using TSMC 90nm CMOS process technology, our design can achieve 2000MHz, and the area cost is reduced by 15.72% as compared to a state-of-the-art design.
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U2 - 10.1109/TCSII.2019.2936230
DO - 10.1109/TCSII.2019.2936230
M3 - Article
AN - SCOPUS:85087443575
VL - 67
SP - 1329
EP - 1333
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
SN - 1549-7747
IS - 7
M1 - 8807317
ER -