A novel ESD device structure with fully silicide process for mixed high/low voltage operation

Jian Hsing Lee, J. R. Shih, Dao Hong Yang, Jone F. Chen, Kenneth Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A novel ESD device structure with non-LDD at drain region has been demonstrated to enhance the ESD immunity of IO circuits with mixed high/low operation voltage. The protection capability of this novel ESD device structure has been proved from 1μm to 65nm technologies with and without fully salicide at the source/drain region. This structure is found to be also very effective to protect the high voltage tolerant (HVT) IO circuits and the drain extended NMOSFET (DEMOS) transistors. The ESD failure thresholds can be improved from HBM < 0.5KV and MM < 50V to HBM 4KV and MM 200V, respectively. In addition, this novel ESD device structure is cost effective because two process modules including RPO and ESD implant can be removed.

Original languageEnglish
Title of host publication2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
DOIs
Publication statusPublished - 2008 Sep 23
Event2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA - Singapore, Singapore
Duration: 2008 Jul 72008 Jul 11

Publication series

NameProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Other

Other2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
CountrySingapore
CitySingapore
Period08-07-0708-07-11

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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