A novel ESD device structure with fully silicide process for mixed high/low voltage operation

Jian Hsing Lee; J. R. Shih; Dao Hong Yang; Jone F. Chen; Kenneth Wu

doi:10.1109/IPFA.2008.4588153

A novel ESD device structure with fully silicide process for mixed high/low voltage operation

Jian Hsing Lee, J. R. Shih, Dao Hong Yang, Jone F. Chen, Kenneth Wu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

A novel ESD device structure with non-LDD at drain region has been demonstrated to enhance the ESD immunity of IO circuits with mixed high/low operation voltage. The protection capability of this novel ESD device structure has been proved from 1μm to 65nm technologies with and without fully salicide at the source/drain region. This structure is found to be also very effective to protect the high voltage tolerant (HVT) IO circuits and the drain extended NMOSFET (DEMOS) transistors. The ESD failure thresholds can be improved from HBM < 0.5KV and MM < 50V to HBM 4KV and MM 200V, respectively. In addition, this novel ESD device structure is cost effective because two process modules including RPO and ESD implant can be removed.

Original language	English
Title of host publication	2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
DOIs	https://doi.org/10.1109/IPFA.2008.4588153
Publication status	Published - 2008 Sept 23
Event	2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA - Singapore, Singapore Duration: 2008 Jul 7 → 2008 Jul 11

Publication series

Name	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Other

Other	2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
Country/Territory	Singapore
City	Singapore
Period	08-07-07 → 08-07-11

All Science Journal Classification (ASJC) codes

Engineering(all)

Access to Document

10.1109/IPFA.2008.4588153

Cite this

Lee, J. H., Shih, J. R., Yang, D. H., Chen, J. F., & Wu, K. (2008). A novel ESD device structure with fully silicide process for mixed high/low voltage operation. In 2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA [4588153] (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). https://doi.org/10.1109/IPFA.2008.4588153

Lee, Jian Hsing ; Shih, J. R. ; Yang, Dao Hong et al. / A novel ESD device structure with fully silicide process for mixed high/low voltage operation. 2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA. 2008. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

@inproceedings{158f3c57fdaf4cabaeafc0af232bdca1,

title = "A novel ESD device structure with fully silicide process for mixed high/low voltage operation",

abstract = "A novel ESD device structure with non-LDD at drain region has been demonstrated to enhance the ESD immunity of IO circuits with mixed high/low operation voltage. The protection capability of this novel ESD device structure has been proved from 1μm to 65nm technologies with and without fully salicide at the source/drain region. This structure is found to be also very effective to protect the high voltage tolerant (HVT) IO circuits and the drain extended NMOSFET (DEMOS) transistors. The ESD failure thresholds can be improved from HBM < 0.5KV and MM < 50V to HBM 4KV and MM 200V, respectively. In addition, this novel ESD device structure is cost effective because two process modules including RPO and ESD implant can be removed.",

author = "Lee, {Jian Hsing} and Shih, {J. R.} and Yang, {Dao Hong} and Chen, {Jone F.} and Kenneth Wu",

year = "2008",

month = sep,

day = "23",

doi = "10.1109/IPFA.2008.4588153",

language = "English",

isbn = "1424420393",

series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",

booktitle = "2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",

note = "2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA ; Conference date: 07-07-2008 Through 11-07-2008",

}

Lee, JH, Shih, JR, Yang, DH, Chen, JF & Wu, K 2008, A novel ESD device structure with fully silicide process for mixed high/low voltage operation. in 2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA., 4588153, Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, 2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, Singapore, Singapore, 08-07-07. https://doi.org/10.1109/IPFA.2008.4588153

A novel ESD device structure with fully silicide process for mixed high/low voltage operation. / Lee, Jian Hsing; Shih, J. R.; Yang, Dao Hong et al.
2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA. 2008. 4588153 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A novel ESD device structure with fully silicide process for mixed high/low voltage operation

AU - Lee, Jian Hsing

AU - Shih, J. R.

AU - Yang, Dao Hong

AU - Chen, Jone F.

AU - Wu, Kenneth

PY - 2008/9/23

Y1 - 2008/9/23

N2 - A novel ESD device structure with non-LDD at drain region has been demonstrated to enhance the ESD immunity of IO circuits with mixed high/low operation voltage. The protection capability of this novel ESD device structure has been proved from 1μm to 65nm technologies with and without fully salicide at the source/drain region. This structure is found to be also very effective to protect the high voltage tolerant (HVT) IO circuits and the drain extended NMOSFET (DEMOS) transistors. The ESD failure thresholds can be improved from HBM < 0.5KV and MM < 50V to HBM 4KV and MM 200V, respectively. In addition, this novel ESD device structure is cost effective because two process modules including RPO and ESD implant can be removed.

AB - A novel ESD device structure with non-LDD at drain region has been demonstrated to enhance the ESD immunity of IO circuits with mixed high/low operation voltage. The protection capability of this novel ESD device structure has been proved from 1μm to 65nm technologies with and without fully salicide at the source/drain region. This structure is found to be also very effective to protect the high voltage tolerant (HVT) IO circuits and the drain extended NMOSFET (DEMOS) transistors. The ESD failure thresholds can be improved from HBM < 0.5KV and MM < 50V to HBM 4KV and MM 200V, respectively. In addition, this novel ESD device structure is cost effective because two process modules including RPO and ESD implant can be removed.

UR - http://www.scopus.com/inward/record.url?scp=51949115723&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=51949115723&partnerID=8YFLogxK

U2 - 10.1109/IPFA.2008.4588153

DO - 10.1109/IPFA.2008.4588153

M3 - Conference contribution

AN - SCOPUS:51949115723

SN - 1424420393

SN - 9781424420391

T3 - Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

BT - 2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

T2 - 2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Y2 - 7 July 2008 through 11 July 2008

ER -

Lee JH, Shih JR, Yang DH, Chen JF, Wu K. A novel ESD device structure with fully silicide process for mixed high/low voltage operation. In 2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA. 2008. 4588153. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). doi: 10.1109/IPFA.2008.4588153

A novel ESD device structure with fully silicide process for mixed high/low voltage operation

Abstract

Publication series

Other

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this