A novel noise margin model of surrounding-gate MOSFET working on subthreshold CMOS logic gates

Tc Kuang Chiang, Chen Chih Yo, Hong Wun Gao, Yeong Her Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we present a novel noise margin model of surrounding-gate MOSFET working on subthreshold CMOS logic gates. Based on the device physics and equivalent transistor model, theoretical analysis of noise margin for SRG MOSFET operating in low-voltage condition is revealed. It is shown that the device parameters such as the thick silicon thickness tsi, thick gate oxide thickness tox, short channel length Lg, and low supply voltage Vdd can severely degrade the noise margin NM. On the contrary, the small subthreshold slope induced by device parameters can suppress the NM degradation efficiently. Being similar to DIBL, NM degraded by the device parameters can also be uniquely determined and controlled by the scaling factor according to scaling theory.

Original languageEnglish
Title of host publication7th IEEE International Nanoelectronics Conference 2016, INEC 2016
PublisherIEEE Computer Society
ISBN (Electronic)9781467389693
DOIs
Publication statusPublished - 2016 Oct 12
Event7th IEEE International Nanoelectronics Conference, INEC 2016 - Chengdu, China
Duration: 2016 May 92016 May 11

Publication series

NameProceedings - International NanoElectronics Conference, INEC
Volume2016-October
ISSN (Print)2159-3523

Other

Other7th IEEE International Nanoelectronics Conference, INEC 2016
CountryChina
CityChengdu
Period16-05-0916-05-11

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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