TY - GEN
T1 - A novel noise margin model of surrounding-gate MOSFET working on subthreshold CMOS logic gates
AU - Chiang, Tc Kuang
AU - Yo, Chen Chih
AU - Gao, Hong Wun
AU - Wang, Yeong Her
PY - 2016/10/12
Y1 - 2016/10/12
N2 - In this paper, we present a novel noise margin model of surrounding-gate MOSFET working on subthreshold CMOS logic gates. Based on the device physics and equivalent transistor model, theoretical analysis of noise margin for SRG MOSFET operating in low-voltage condition is revealed. It is shown that the device parameters such as the thick silicon thickness tsi, thick gate oxide thickness tox, short channel length Lg, and low supply voltage Vdd can severely degrade the noise margin NM. On the contrary, the small subthreshold slope induced by device parameters can suppress the NM degradation efficiently. Being similar to DIBL, NM degraded by the device parameters can also be uniquely determined and controlled by the scaling factor according to scaling theory.
AB - In this paper, we present a novel noise margin model of surrounding-gate MOSFET working on subthreshold CMOS logic gates. Based on the device physics and equivalent transistor model, theoretical analysis of noise margin for SRG MOSFET operating in low-voltage condition is revealed. It is shown that the device parameters such as the thick silicon thickness tsi, thick gate oxide thickness tox, short channel length Lg, and low supply voltage Vdd can severely degrade the noise margin NM. On the contrary, the small subthreshold slope induced by device parameters can suppress the NM degradation efficiently. Being similar to DIBL, NM degraded by the device parameters can also be uniquely determined and controlled by the scaling factor according to scaling theory.
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U2 - 10.1109/INEC.2016.7589363
DO - 10.1109/INEC.2016.7589363
M3 - Conference contribution
AN - SCOPUS:84992679772
T3 - Proceedings - International NanoElectronics Conference, INEC
BT - 7th IEEE International Nanoelectronics Conference 2016, INEC 2016
PB - IEEE Computer Society
T2 - 7th IEEE International Nanoelectronics Conference, INEC 2016
Y2 - 9 May 2016 through 11 May 2016
ER -