TY - GEN
T1 - A novel test generation method for small-delay defects with user-defined fault model
AU - Shang, Chao Jun
AU - Wu, Cheng Hung
AU - Lee, Kuen Jong
AU - Chen, Yu Hsiang
PY - 2019/4
Y1 - 2019/4
N2 - To ensure the quality of high-performance VLSI chips, small delay defects (SDDs) are widely considered in the industry. Several ATPG tools have been developed to deal with these defects, with timing information employed to help select long paths that are more sensitive to small delays and hence high-quality tests can be generated. However, these methods usually result in a large pattern count or cannot achieve high test coverage (DTC). In this paper, we propose a novel test generation method for SDDs based on a common path stem concept. By extracting the common path stems of those long paths in a circuit, one can use the user-defined fault model (UDFM) to set some conditions on the path stems and thus force the fault effects of SDDs to propagate through long paths, such that a compact pattern set can be generated and high DTC can be achieved for SDDs. Compared with the well-known timing-aware ATPG, our proposed method can reduce 19.2% pattern count and increase 0.74% DTC on average for ISCAS89 and IWLS05 benchmark circuits.
AB - To ensure the quality of high-performance VLSI chips, small delay defects (SDDs) are widely considered in the industry. Several ATPG tools have been developed to deal with these defects, with timing information employed to help select long paths that are more sensitive to small delays and hence high-quality tests can be generated. However, these methods usually result in a large pattern count or cannot achieve high test coverage (DTC). In this paper, we propose a novel test generation method for SDDs based on a common path stem concept. By extracting the common path stems of those long paths in a circuit, one can use the user-defined fault model (UDFM) to set some conditions on the path stems and thus force the fault effects of SDDs to propagate through long paths, such that a compact pattern set can be generated and high DTC can be achieved for SDDs. Compared with the well-known timing-aware ATPG, our proposed method can reduce 19.2% pattern count and increase 0.74% DTC on average for ISCAS89 and IWLS05 benchmark circuits.
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U2 - 10.1109/VLSI-DAT.2019.8741773
DO - 10.1109/VLSI-DAT.2019.8741773
M3 - Conference contribution
T3 - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
BT - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
Y2 - 22 April 2019 through 25 April 2019
ER -