Abstract
To ensure the quality of high-performance VLSI chips, small delay defects (SDDs) are widely considered in the industry. Several ATPG tools have been developed to deal with these defects, with timing information employed to help select long paths that are more sensitive to small delays and hence high-quality tests can be generated. However, these methods usually result in a large pattern count or cannot achieve high test coverage (DTC). In this paper, we propose a novel test generation method for SDDs based on a common path stem concept. By extracting the common path stems of those long paths in a circuit, one can use the user-defined fault model (UDFM) to set some conditions on the path stems and thus force the fault effects of SDDs to propagate through long paths, such that a compact pattern set can be generated and high DTC can be achieved for SDDs. Compared with the well-known timing-aware ATPG, our proposed method can reduce 19.2% pattern count and increase 0.74% DTC on average for ISCAS89 and IWLS05 benchmark circuits.
| Original language | English |
|---|---|
| Title of host publication | 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9781728106557 |
| DOIs | |
| Publication status | Published - 2019 Apr 1 |
| Event | 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 - Hsinchu, Taiwan Duration: 2019 Apr 22 → 2019 Apr 25 |
Publication series
| Name | 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 |
|---|
Conference
| Conference | 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 |
|---|---|
| Country | Taiwan |
| City | Hsinchu |
| Period | 19-04-22 → 19-04-25 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality
- Instrumentation
- Computer Networks and Communications
- Hardware and Architecture
Cite this
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A novel test generation method for small-delay defects with user-defined fault model. / Shang, Chao Jun; Wu, Cheng Hung; Lee, Kuen-Jong; Chen, Yu Hsiang.
2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8741773 (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - A novel test generation method for small-delay defects with user-defined fault model
AU - Shang, Chao Jun
AU - Wu, Cheng Hung
AU - Lee, Kuen-Jong
AU - Chen, Yu Hsiang
PY - 2019/4/1
Y1 - 2019/4/1
N2 - To ensure the quality of high-performance VLSI chips, small delay defects (SDDs) are widely considered in the industry. Several ATPG tools have been developed to deal with these defects, with timing information employed to help select long paths that are more sensitive to small delays and hence high-quality tests can be generated. However, these methods usually result in a large pattern count or cannot achieve high test coverage (DTC). In this paper, we propose a novel test generation method for SDDs based on a common path stem concept. By extracting the common path stems of those long paths in a circuit, one can use the user-defined fault model (UDFM) to set some conditions on the path stems and thus force the fault effects of SDDs to propagate through long paths, such that a compact pattern set can be generated and high DTC can be achieved for SDDs. Compared with the well-known timing-aware ATPG, our proposed method can reduce 19.2% pattern count and increase 0.74% DTC on average for ISCAS89 and IWLS05 benchmark circuits.
AB - To ensure the quality of high-performance VLSI chips, small delay defects (SDDs) are widely considered in the industry. Several ATPG tools have been developed to deal with these defects, with timing information employed to help select long paths that are more sensitive to small delays and hence high-quality tests can be generated. However, these methods usually result in a large pattern count or cannot achieve high test coverage (DTC). In this paper, we propose a novel test generation method for SDDs based on a common path stem concept. By extracting the common path stems of those long paths in a circuit, one can use the user-defined fault model (UDFM) to set some conditions on the path stems and thus force the fault effects of SDDs to propagate through long paths, such that a compact pattern set can be generated and high DTC can be achieved for SDDs. Compared with the well-known timing-aware ATPG, our proposed method can reduce 19.2% pattern count and increase 0.74% DTC on average for ISCAS89 and IWLS05 benchmark circuits.
UR - http://www.scopus.com/inward/record.url?scp=85068624563&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85068624563&partnerID=8YFLogxK
U2 - 10.1109/VLSI-DAT.2019.8741773
DO - 10.1109/VLSI-DAT.2019.8741773
M3 - Conference contribution
AN - SCOPUS:85068624563
T3 - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
BT - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
PB - Institute of Electrical and Electronics Engineers Inc.
ER -