A novel test methodology based on error-rate to support error-tolerance

Kuen-Jong Lee, Tong Y. Hsieh, Melvin A. Breuer

Research output: Chapter in Book/Report/Conference proceedingConference contribution

45 Citations (Scopus)


As the advance of VLSI technology approaches physical limitations, the yield associated with high performance system-on-chip (SOC) designs will continue to decline. Conventional methodologies to address this problem, such as fault-tolerance and defect-tolerance, may become inadequate. Recently, the concept of error-tolerance has drawn much attention. Under this new concept, some defective chips (or systems) can still be labeled as acceptable, i.e., marketable, even if some outputted results are erroneous. The motivation for employing error-tolerance is to significantly increase the effective yield of some chips when used in certain applications. In this paper, we propose a novel error-rate based test methodology to support the notion of error-tolerance. Several definitions, such as various measures of yields, individual-fault and system error-rates, defect level and unacceptable defect levels are clarified or redefined. Analytically derived measures are formulated to estimate the error-rate associated with a fault, and to generate lists of faults that are acceptable with respect to a specified upper bound on the system error-rate. These results include consideration of the degree of confidence of an estimate, and provide a theoretic basis that enables the practical application of the concept of error-tolerance to both test set reduction and yield improvement. Experimental results show that the proposed test methodology can easily identify a set of acceptable faults, i.e., faults that might occur but need not cause the part to be discarded. The increase in effective yield depends on requirements imposed by end users. We show that a significant improvement in effective yield can be achieved for some applications.

Original languageEnglish
Title of host publicationIEEE International Test Conference, Proceedings, ITC 2005
Number of pages9
Publication statusPublished - 2005
EventIEEE International Test Conference, ITC 2005 - Austin, TX, United States
Duration: 2005 Nov 82005 Nov 10


OtherIEEE International Test Conference, ITC 2005
Country/TerritoryUnited States
CityAustin, TX

All Science Journal Classification (ASJC) codes

  • Engineering(all)


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