A parallel built-in diagnostic scheme for multiple embedded memories

Li Ming Denq, Rei Fu Huang, Cheng Wen Wu, Yeong Jar Chang, Wen Ching Wu

Research output: Contribution to journalConference article

1 Citation (Scopus)

Abstract

Hundreds of memory cores can be found on a typical system-on-chip (SOC) today. Diagnosing such a large number of memory cores using a conventional built-in self-test (BIST) architecture consumes too much time, as its on-chip diagnostics support is for sequential diagnosis only. In this paper, we present a memory BIST architecture with parallel diagnosis scheme. The proposed parallel built-in self-diagnosis (PBISD) scheme was developed to work with our existing Memory Optimization and REconfiguration (MORE) system, which configures small memory cores into the large one specified by the user, subject to the power and geometry constraints. With PBISD and MORE, memory test and diagnosis can be done in a much shorter time, and the whole system provides a good balance among test time, test power, and test hardware overhead. Experimental results show that, when compared with a conventional BISD scheme, the diagnosis time for a case with four memory cores is only 25%. Moreover, the area overhead is only 49%, as only one test pattern generator is required.

Original languageEnglish
Pages (from-to)65-69
Number of pages5
JournalRecords of the IEEE International Workshop on Memory Technology, Design and Testing
Publication statusPublished - 2004 Dec 17
EventRecords of the 2004 International Workshop on Memory Technology, Design and Testing, MTDT 2004 - San Jose, CA, United States
Duration: 2004 Aug 92004 Aug 10

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Data storage equipment
Built-in self test
Computer systems
Hardware
Geometry

All Science Journal Classification (ASJC) codes

  • Media Technology

Cite this

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title = "A parallel built-in diagnostic scheme for multiple embedded memories",
abstract = "Hundreds of memory cores can be found on a typical system-on-chip (SOC) today. Diagnosing such a large number of memory cores using a conventional built-in self-test (BIST) architecture consumes too much time, as its on-chip diagnostics support is for sequential diagnosis only. In this paper, we present a memory BIST architecture with parallel diagnosis scheme. The proposed parallel built-in self-diagnosis (PBISD) scheme was developed to work with our existing Memory Optimization and REconfiguration (MORE) system, which configures small memory cores into the large one specified by the user, subject to the power and geometry constraints. With PBISD and MORE, memory test and diagnosis can be done in a much shorter time, and the whole system provides a good balance among test time, test power, and test hardware overhead. Experimental results show that, when compared with a conventional BISD scheme, the diagnosis time for a case with four memory cores is only 25{\%}. Moreover, the area overhead is only 49{\%}, as only one test pattern generator is required.",
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A parallel built-in diagnostic scheme for multiple embedded memories. / Denq, Li Ming; Huang, Rei Fu; Wu, Cheng Wen; Chang, Yeong Jar; Wu, Wen Ching.

In: Records of the IEEE International Workshop on Memory Technology, Design and Testing, 17.12.2004, p. 65-69.

Research output: Contribution to journalConference article

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AU - Denq, Li Ming

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