A pipelined SAR ADC with loading-separating technique in 90-nm CMOS technology

Sheng Hsiung Lin, Jin Fu Lin, Guan Ying Huang, Soon Jyh Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents a 12-bit 50-MS/s pipelined SAR analog-to-digital converter (ADC) with loading-separating technique. The proposed loading-separating technique relaxes output loading of multiplying digital-to-analog converter (MDAC) and increases the time budget of bit cycling for the 2nd stage. In addition, a split-path amplification MDAC is proposed to enhance amplifier's gain and bandwidth. The ADC core occupies an active area of 0.27 mm2 in TSMC 90-nm 1P9M CMOS process. The measured results show that the proposed ADC achieves 63.56 dB SNDR with 2.17 mW power consumption.

Original languageEnglish
Title of host publication2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
Pages264-267
Number of pages4
DOIs
Publication statusPublished - 2012 Dec 1
Event2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012 - Kaohsiung, Taiwan
Duration: 2012 Dec 22012 Dec 5

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

Other2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
CountryTaiwan
CityKaohsiung
Period12-12-0212-12-05

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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