A planarized shallow-trench-isolation for GaAs devices fabrication using liquid phase chemical enhanced oxidation process

Jau Yi Wu; Hwei Heng Wang; Po Wen Sze; Yeong Her Wang; Mau Phon Houng

doi:10.1109/55.998862

A planarized shallow-trench-isolation for GaAs devices fabrication using liquid phase chemical enhanced oxidation process

Jau Yi Wu, Hwei Heng Wang, Po Wen Sze, Yeong Her Wang, Mau Phon Houng

Research output: Contribution to journal › Letter › peer-review

10 Citations (Scopus)

Abstract

A new planarized trench isolation technique for GaAs devices fabrication by a liquid phase chemical-enhanced oxidation (LPCEO) method is proposed. The LPCEO-trench-isolation technique can be operated at low temperature with a simple and low-cost process. As compared with conventional mesa isolation, the LPCEO-trench-isolation can provide better planarity and isolation properties. Finally, GaAs MOSFET's fabricated with LPCEO-trench-isolation and selective oxidized gate both by the LPCEO method are demonstrated.

Original language	English
Pages (from-to)	237-239
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	23
Issue number	5
DOIs	https://doi.org/10.1109/55.998862
Publication status	Published - 2002 May

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/55.998862

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title = "A planarized shallow-trench-isolation for GaAs devices fabrication using liquid phase chemical enhanced oxidation process",

abstract = "A new planarized trench isolation technique for GaAs devices fabrication by a liquid phase chemical-enhanced oxidation (LPCEO) method is proposed. The LPCEO-trench-isolation technique can be operated at low temperature with a simple and low-cost process. As compared with conventional mesa isolation, the LPCEO-trench-isolation can provide better planarity and isolation properties. Finally, GaAs MOSFET's fabricated with LPCEO-trench-isolation and selective oxidized gate both by the LPCEO method are demonstrated.",

author = "Wu, {Jau Yi} and Wang, {Hwei Heng} and Sze, {Po Wen} and Wang, {Yeong Her} and Houng, {Mau Phon}",

note = "Funding Information: Manuscript received December 17, 2001. This work was supported in part by the National Science Council of Taiwan, R.O.C., under Contracts NSC 89-2215-E-244-001 and NSC 89-2219-E-006-025, and the Foundation of Chen, Jieh-Chen Scholarship, Tainan, Taiwan, R.O.C. The review of this letter was arranged by Editor D. Ueda.",

year = "2002",

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language = "English",

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pages = "237--239",

journal = "IEEE Electron Device Letters",

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T1 - A planarized shallow-trench-isolation for GaAs devices fabrication using liquid phase chemical enhanced oxidation process

AU - Wu, Jau Yi

AU - Wang, Hwei Heng

AU - Sze, Po Wen

AU - Wang, Yeong Her

AU - Houng, Mau Phon

N1 - Funding Information: Manuscript received December 17, 2001. This work was supported in part by the National Science Council of Taiwan, R.O.C., under Contracts NSC 89-2215-E-244-001 and NSC 89-2219-E-006-025, and the Foundation of Chen, Jieh-Chen Scholarship, Tainan, Taiwan, R.O.C. The review of this letter was arranged by Editor D. Ueda.

PY - 2002/5

Y1 - 2002/5

N2 - A new planarized trench isolation technique for GaAs devices fabrication by a liquid phase chemical-enhanced oxidation (LPCEO) method is proposed. The LPCEO-trench-isolation technique can be operated at low temperature with a simple and low-cost process. As compared with conventional mesa isolation, the LPCEO-trench-isolation can provide better planarity and isolation properties. Finally, GaAs MOSFET's fabricated with LPCEO-trench-isolation and selective oxidized gate both by the LPCEO method are demonstrated.

AB - A new planarized trench isolation technique for GaAs devices fabrication by a liquid phase chemical-enhanced oxidation (LPCEO) method is proposed. The LPCEO-trench-isolation technique can be operated at low temperature with a simple and low-cost process. As compared with conventional mesa isolation, the LPCEO-trench-isolation can provide better planarity and isolation properties. Finally, GaAs MOSFET's fabricated with LPCEO-trench-isolation and selective oxidized gate both by the LPCEO method are demonstrated.

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JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 5

ER -

A planarized shallow-trench-isolation for GaAs devices fabrication using liquid phase chemical enhanced oxidation process

Abstract

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