A planarized shallow-trench-isolation for GaAs devices fabrication using liquid phase chemical enhanced oxidation process

Jau Yi Wu, Hwei Heng Wang, Po Wen Sze, Yeong-Her Wang, Mau-phon Houng

Research output: Contribution to journalLetter

9 Citations (Scopus)

Abstract

A new planarized trench isolation technique for GaAs devices fabrication by a liquid phase chemical-enhanced oxidation (LPCEO) method is proposed. The LPCEO-trench-isolation technique can be operated at low temperature with a simple and low-cost process. As compared with conventional mesa isolation, the LPCEO-trench-isolation can provide better planarity and isolation properties. Finally, GaAs MOSFET's fabricated with LPCEO-trench-isolation and selective oxidized gate both by the LPCEO method are demonstrated.

Original languageEnglish
Pages (from-to)237-239
Number of pages3
JournalIEEE Electron Device Letters
Volume23
Issue number5
DOIs
Publication statusPublished - 2002 May 1

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Fabrication
Oxidation
Liquids
gallium arsenide
Costs
Temperature

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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title = "A planarized shallow-trench-isolation for GaAs devices fabrication using liquid phase chemical enhanced oxidation process",
abstract = "A new planarized trench isolation technique for GaAs devices fabrication by a liquid phase chemical-enhanced oxidation (LPCEO) method is proposed. The LPCEO-trench-isolation technique can be operated at low temperature with a simple and low-cost process. As compared with conventional mesa isolation, the LPCEO-trench-isolation can provide better planarity and isolation properties. Finally, GaAs MOSFET's fabricated with LPCEO-trench-isolation and selective oxidized gate both by the LPCEO method are demonstrated.",
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A planarized shallow-trench-isolation for GaAs devices fabrication using liquid phase chemical enhanced oxidation process. / Wu, Jau Yi; Wang, Hwei Heng; Sze, Po Wen; Wang, Yeong-Her; Houng, Mau-phon.

In: IEEE Electron Device Letters, Vol. 23, No. 5, 01.05.2002, p. 237-239.

Research output: Contribution to journalLetter

TY - JOUR

T1 - A planarized shallow-trench-isolation for GaAs devices fabrication using liquid phase chemical enhanced oxidation process

AU - Wu, Jau Yi

AU - Wang, Hwei Heng

AU - Sze, Po Wen

AU - Wang, Yeong-Her

AU - Houng, Mau-phon

PY - 2002/5/1

Y1 - 2002/5/1

N2 - A new planarized trench isolation technique for GaAs devices fabrication by a liquid phase chemical-enhanced oxidation (LPCEO) method is proposed. The LPCEO-trench-isolation technique can be operated at low temperature with a simple and low-cost process. As compared with conventional mesa isolation, the LPCEO-trench-isolation can provide better planarity and isolation properties. Finally, GaAs MOSFET's fabricated with LPCEO-trench-isolation and selective oxidized gate both by the LPCEO method are demonstrated.

AB - A new planarized trench isolation technique for GaAs devices fabrication by a liquid phase chemical-enhanced oxidation (LPCEO) method is proposed. The LPCEO-trench-isolation technique can be operated at low temperature with a simple and low-cost process. As compared with conventional mesa isolation, the LPCEO-trench-isolation can provide better planarity and isolation properties. Finally, GaAs MOSFET's fabricated with LPCEO-trench-isolation and selective oxidized gate both by the LPCEO method are demonstrated.

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JF - IEEE Electron Device Letters

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