A power-efficient pulse-based in-situ timing error predictor for PVT-variation sensitive circuits

Lih-Yih Chiou; Chi Ray Huang; Ming Hung Wu

doi:10.1109/ISCAS.2014.6865360

A power-efficient pulse-based in-situ timing error predictor for PVT-variation sensitive circuits

Lih-Yih Chiou, Chi Ray Huang, Ming Hung Wu

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

Adaptive design is one of the most promising approaches for mitigating the large design margin used by dynamically scaling the supply voltage and frequency of integrated circuits. A low cost and power efficient variation detection circuit is one of the critical components intended to achieve the goal of adaptive control. In this paper, we proposed a pulse-based timing error prediction mechanism that can minimize safety margins with low design overhead. When compared with the conventional canary-based circuit technique, 28.7% power reduction is achieved under 50% data activity. Moreover, an average of 48.3% power reduction is obtained across different process corners at ultra-low voltage regime as compared to the worst case design.

Original language	English
Title of host publication	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1215-1218
Number of pages	4
ISBN (Print)	9781479934324
DOIs	https://doi.org/10.1109/ISCAS.2014.6865360
Publication status	Published - 2014 Jan 1
Event	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia Duration: 2014 Jun 1 → 2014 Jun 5

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Other

Other	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Country	Australia
City	Melbourne, VIC
Period	14-06-01 → 14-06-05

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2014.6865360

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Chiou, L-Y., Huang, C. R., & Wu, M. H. (2014). A power-efficient pulse-based in-situ timing error predictor for PVT-variation sensitive circuits. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 (pp. 1215-1218). [6865360] (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2014.6865360

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Chiou, L-Y, Huang, CR & Wu, MH 2014, A power-efficient pulse-based in-situ timing error predictor for PVT-variation sensitive circuits. in 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014., 6865360, Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., pp. 1215-1218, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014, Melbourne, VIC, Australia, 14-06-01. https://doi.org/10.1109/ISCAS.2014.6865360

A power-efficient pulse-based in-situ timing error predictor for PVT-variation sensitive circuits. / Chiou, Lih-Yih; Huang, Chi Ray; Wu, Ming Hung.

2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., 2014. p. 1215-1218 6865360 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - Adaptive design is one of the most promising approaches for mitigating the large design margin used by dynamically scaling the supply voltage and frequency of integrated circuits. A low cost and power efficient variation detection circuit is one of the critical components intended to achieve the goal of adaptive control. In this paper, we proposed a pulse-based timing error prediction mechanism that can minimize safety margins with low design overhead. When compared with the conventional canary-based circuit technique, 28.7% power reduction is achieved under 50% data activity. Moreover, an average of 48.3% power reduction is obtained across different process corners at ultra-low voltage regime as compared to the worst case design.

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Chiou L-Y, Huang CR, Wu MH. A power-efficient pulse-based in-situ timing error predictor for PVT-variation sensitive circuits. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc. 2014. p. 1215-1218. 6865360. (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2014.6865360