@inproceedings{e0bd1a4d443241aa9e356eb5da6734d1,
title = "A power-efficient pulse-based in-situ timing error predictor for PVT-variation sensitive circuits",
abstract = "Adaptive design is one of the most promising approaches for mitigating the large design margin used by dynamically scaling the supply voltage and frequency of integrated circuits. A low cost and power efficient variation detection circuit is one of the critical components intended to achieve the goal of adaptive control. In this paper, we proposed a pulse-based timing error prediction mechanism that can minimize safety margins with low design overhead. When compared with the conventional canary-based circuit technique, 28.7% power reduction is achieved under 50% data activity. Moreover, an average of 48.3% power reduction is obtained across different process corners at ultra-low voltage regime as compared to the worst case design.",
author = "Chiou, {Lih Yih} and Huang, {Chi Ray} and Wu, {Ming Hung}",
year = "2014",
doi = "10.1109/ISCAS.2014.6865360",
language = "English",
isbn = "9781479934324",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1215--1218",
booktitle = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014",
address = "United States",
note = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 ; Conference date: 01-06-2014 Through 05-06-2014",
}