A Processor and Cache Online Self-Testing Methodology for OS-Managed Platform

Ching Wen Lin, Chung Ho Chen

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)

Abstract

Software-based self-test (SBST) is an effective method to detect operational faults of a processor system. We propose an architectural approach to support high fault-coverage online SBST: Processor Shield, which tackles the difficult-to-test issues raised due to the protection of an operating system. The processor shield, including a software framework and design for testing hardware, creates an online self-testing environment without influencing other processes and on-bus devices even if the SBST fails. We present a case study that demonstrates SBST executions under Linux kernel on an ARMv5-compatible processor system. For CPU testing, the stuck-at fault coverage is over 99% while the transition fault coverage is higher than 93%. For cache control logic testing, the stuck-at fault coverage is over 99% while the transition fault coverage is higher than 95%. For RAM module testing, the fault coverage is nearly 100%. Cache SBSTs finish in a context-switch interval of less than 4 ms while CPU SBST finishes in less than 8 ms for 1-GHz clock. The hardware overhead of the processor shield is only 0.494% of the whole processor area. We also present an SBST-dynamic voltage and frequency scaling application that calibrates the dynamic minimal guardbands and helps achieving lower power consumption and mitigating transistor-aging effect.

Original languageEnglish
Article number7924426
Pages (from-to)2346-2359
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume25
Issue number8
DOIs
Publication statusPublished - 2017 Aug

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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