A processor-based built-in self-repair design for embedded memories

Chin Lung Su, Rei Fu Huang, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

30 Citations (Scopus)

Abstract

We propose an embedded processor-based built-in self-repair (BISR) design for embedded memories. In the proposed design we reuse the embedded processor that can be found on almost every system-on-chip (SOC) product, in addition to many distinct features. By reusing the embedded processor, the controller and redundancy analysis circuit of a typical BISR design can be removed. Also, the test algorithm and redundancy analysis/allocation algorithm are easily programmable, greatly increasing the design flexibility. We also have developed a memory wrapper that allows at-speed testing of the memory cores. The area overhead of the proposed BISR scheme is low, since only the memory wrapper needs to be realized explicitly. Our experiments show that the BISR area overhead for a typical 8Kx32 SRAM is lower than 1%.

Original languageEnglish
Title of host publicationProceedings - 12th Asian Test Symposium, ATS 2003
PublisherIEEE Computer Society
Pages366-371
Number of pages6
ISBN (Electronic)0769519512
DOIs
Publication statusPublished - 2003 Jan 1
Event12th Asian Test Symposium, ATS 2003 - Xi'an, China
Duration: 2003 Nov 162003 Nov 19

Publication series

NameProceedings of the Asian Test Symposium
Volume2003-January
ISSN (Print)1081-7735

Other

Other12th Asian Test Symposium, ATS 2003
CountryChina
CityXi'an
Period03-11-1603-11-19

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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