A processor shield for software-based on-line self-test

Ching Wen Lin, Chung Ho Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Software-based processor self-test typically ignores system related testing issues such as interrupt, memory-mapped IOs, especially for on-line testing. We propose an architectural support for processor SBST testing: Processor Shield, which can tackle the difficult-to-test issues during on-line SBST. We develop an execution flow to control the processor shield and run the SBST program without interfering other processes and on-bus devices. Finally, we present a case study that executes the SBST program under Linux kernel on an ARMv5-compatible processor system. Our method can successfully switch the test process and the kernel process and achieve the expected high processor fault coverage. The hardware overhead of the processor shield is 2.6% compared to the logic part of the processor.

Original languageEnglish
Title of host publication2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages149-152
Number of pages4
ISBN (Electronic)9781509015702
DOIs
Publication statusPublished - 2017 Jan 3
Event2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 - Jeju, Korea, Republic of
Duration: 2016 Oct 252016 Oct 28

Publication series

Name2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016

Other

Other2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
CountryKorea, Republic of
CityJeju
Period16-10-2516-10-28

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Signal Processing

Fingerprint Dive into the research topics of 'A processor shield for software-based on-line self-test'. Together they form a unique fingerprint.

Cite this