A programmable BIST core for embedded DRAM

Chih Tsun Huang, Jing Reng Huang, Chi Feng Wu, Tsin Yuan Chang, Cheng-Wen Wu

Research output: Contribution to journalArticlepeer-review

98 Citations (Scopus)


The programmable BIST design presented here supports various test modes using a simple controller. With the March C - algorithm, the BIST circuit's overhead is under 1.3% for a 1-Mbit DRAM and under 0.3% for a 16-Mbit DRAM.

Original languageEnglish
Pages (from-to)59-70
Number of pages12
JournalIEEE Design and Test of Computers
Issue number1
Publication statusPublished - 1999 Jan 1

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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