A quick jitter tolerance estimation technique for bang-bang CDRs

Yen Long Lee, Soon Jyh Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Simulating/Measuring the jitter tolerance of clock and data recovery (CDR) circuits, and confirming if the associated jitter tolerance meets the required specification for a specified communication standard, is an important consideration for designing/testing high-speed serial link interface circuits. However, conducting such performance evaluations are costly and time-consuming. In this paper, a simple but effective testing method for evaluating the tracking capability of bang-bang CDR circuits is introduced. The tracking capability of the CDR loop is obtained by simply inverting the recovered clock to produce a 0.5 unit interval (UI) phase shift and capture the tracking time. The proposed technique is easily implemented, because of its fully-digital characteristic, and suitable for testing CDRs that is embedded in a complex interface transceiver. Then, a quick jitter tolerance estimation technique based on the obtained tracking capability is proposed to simplify the time-consuming process as well as avoid the costly test equipment required for designing and/or testing CDR circuits. Experimental results show that the proposed techniques could precisely evaluate the tracking capability and efficiently reduce test costs in acquiring complete jitter tolerance testing.

Original languageEnglish
Title of host publicationITC-Asia 2017 - International Test Conference in Asia
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages8-13
Number of pages6
ISBN (Electronic)9781538630518
DOIs
Publication statusPublished - 2017 Nov 3
Event1st International Test Conference in Asia, ITC-Asia 2017 - Taipei, Taiwan
Duration: 2017 Sep 132017 Sep 15

Publication series

NameITC-Asia 2017 - International Test Conference in Asia

Other

Other1st International Test Conference in Asia, ITC-Asia 2017
CountryTaiwan
CityTaipei
Period17-09-1317-09-15

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Automotive Engineering
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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  • Cite this

    Lee, Y. L., & Chang, S. J. (2017). A quick jitter tolerance estimation technique for bang-bang CDRs. In ITC-Asia 2017 - International Test Conference in Asia (pp. 8-13). [8097101] (ITC-Asia 2017 - International Test Conference in Asia). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ITC-ASIA.2017.8097101